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Visitor
Visitor
7,808 Views
Registered: ‎04-13-2011

risc processor design

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sir

 I have designed a risc processor using verilog.

I am using xilinx ISE 10.1 and spartan 3E fpga kit.I have synthesized and simulated the entire program successfully.But after i have programmed the processor code onto the fpga kit,the outputs are not coming as expected.

I feel that there is some problem with the temporary RAM block or the Program Counter,but i am at complete loss to find the specific location of the problem as the simulation waveforms show the accurate results....

I have attached my code herewith...

Thankyou

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Xilinx Employee
Xilinx Employee
9,932 Views
Registered: ‎01-03-2008

Re: risc processor design

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I took the code that you posted and ran it through XST and it generated 116 WARNINGS including important ones like these:

 

 

WARNING:HDLCompiler:413 - "src/final_add3.v" Line 672: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "src/final_add3.v" Line 673: Result of 32-bit expression is truncated to fit in 8-bit target.

WARNING:HDLCompiler:91 - "src/final_add3.v" Line 209: Signal <PCount> missing in the sensitivity list 

WARNING:Xst:737 - Found 1-bit latch for signal <Exe<6>>. Latches may be generated from incomplete case or if statements
WARNING:Xst:737 - Found 1-bit latch for signal <Exe<5>>. Latches may be generated from incomplete case or if statements
WARNING:Xst:737 - Found 1-bit latch for signal <Exe<4>>. Latches may be generated from incomplete case or if statements

WARNING:Xst:2042 - Unit bips1: 8 internal tristates are replaced by logic (pull-up yes): BusWires<0>, BusWires<1>, BusW
ires<2>, BusWires<3>, BusWires<4>, BusWires<5>, BusWires<6>, BusWires<7>.
WARNING:Xst:2042 - Unit dec2to4: 4 internal tristates are replaced by logic (pull-up yes): Y<0>, Y<1>, Y<2>, Y<3>

 Start by cleaning up your code first and removing most if not all of the WARNINGs (there may be a couple that can't be removed).

 

Start first with the latches that were generated and then the size mismatches.

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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Instructor
Instructor
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Registered: ‎07-21-2009

Re: risc processor design

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Have you been successful loading and running any design onto the Spartan-3E board?

Does the FPGA configure (DONE pin goes 'high')?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer
Observer
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Registered: ‎09-08-2010

Re: risc processor design

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Assuming the FPGA is being programmed correctly, you can use Chipscope to help debug.  Just user the core generator to create a few chipscope ILA modules (there are docs and tutorials all over the web) and instantiate them in your design.  Hook them up to the program counter and your control block state machine.  then you can see if your simulations are actually correct.  case in point, about 5 montsh ago, I had great timulations, but when I synthesized and programmed a FPGA, it didn't behave quite correctly.  Chipscope enabled me to look into the FPGA and check my sim results against what was actually happening in the hardware.

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Visitor
Visitor
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Registered: ‎04-13-2011

Re: risc processor design

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yes sir,i have earlier loaded some programs successfully on the fpga board....it worked correctly,with the done bit going high.....
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Instructor
Instructor
7,789 Views
Registered: ‎07-21-2009

Re: risc processor design

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yes sir,i have earlier loaded some programs successfully on the fpga board....it worked correctly,with the done bit going high.....

OK, with the knowledge that you can successfully program the fpga board, that lets you focus your attention on...

your design!

  • Have you simulated your design?
  • Do you have any asynchronous inputs to state machines in your design?
  • Can you break your design into smaller chunks, to help isolate design problems?

And one more thing.  Please don't call me sir.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor
Visitor
7,784 Views
Registered: ‎04-13-2011

Re: risc processor design

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I am sorry...won't call you sir again....
Have you simulated your design?yes i have using ModelSim and the waveforms are appearing correctly
Do you have any asynchronous inputs to state machines in your design? no

n lastly....i have loaded the modules separately viz Ram,prog counter,Ram & prog counter combined,alu,etc and they are giving correct outputs but.....

in the RAM block code...when loaded on the board,and reset pin is activated,no led should glow indicating value is cleared as is obtained for the other modules, but instead two leds always remain blinking

 

Actually i am very worried,this is my semester project. After all the hard work put on it...if the output does not come out successfully I will be nowhere!!!!:smileysad:

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Instructor
Instructor
7,775 Views
Registered: ‎07-21-2009

risc processor design debugging

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It sounds like you have simulated portions of the design, but you have not simulated the entire design, together.  Is this correct?

in the RAM block code...when loaded on the board,and reset pin is activated,no led should glow indicating value is cleared as is obtained for the other modules, but instead two leds always remain blinking

I do not know your design, or your design structure.  If this is my design, and my project to debug, these are the steps I would take.  I do not know if they apply to your design.

 

1.  Reduce clock frequency to half (or less) of your target operating frequency.  This allows you to eliminate timing problems as a problem source until you have finished debugging the logic in the design.

 

2.  Verify that all resets are de-asserted.

 

3.  Program the RISC processor to toggle an output pin (or LED) on and off, using as few instructions as possible, in a tight loop.

  • If this works, then the basic instruction fetch and execution datapath is working.
  • If not, then copy the program counter bits to external pins which can be probed on the board, and verify that the program counter is running as expected.  Debug the program counter and instruction fetch datapath.

4.  Expand the RISC program to include more of the datapath, more instructions, more of the branch logic.  Add, test/verify, and debug only one additional function or logic block at a time, so that your attention is focused on a small block rather than the entire design.

 

5.  Once you have verified the design at slow operating frequency, then restore system clock to correct operating frequency.  Change nothing else.  If the design works at low speed but not at high speed, this is a sign of a timing problem.  You will need to perform timing analysis and perhaps redesign bits of the code to run at higher clock rates.

 

The important thing is to narrow your debugging attention to a set of code which is as small as possible.  If you have to find a problem which can be anywhere in the design, debugging will take you a very long time.

 

An oscilloscope can be very handy.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Professor
Professor
7,767 Views
Registered: ‎08-14-2007

Re: risc processor design

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Just another point:

 

You say you loaded parts of the design into the hardware.  How do you hook them up?

Did you verify that your .ucf file was actually applied to the partial build, especially

that all of the pins are located in accordance with the board-level hardware?

 

-- Gabor

-- Gabor
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Visitor
Visitor
7,726 Views
Registered: ‎04-13-2011

Re: risc processor design

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i hav loaded and checked both the entitre design and the respective modules separately and have generated correspoding ucf files in the process.....
when i burnt the entire design code..the simulations were successful as expected,but the only problem was that it showed undesired outputs on the board....
So I thought that I should break the entire design into chunks(sepsrate modules viz alu,ram.pc....)to detect the problem,but in that case both the simulation & loading was correct....
S0 i am not being able to detect where the error is....
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Xilinx Employee
Xilinx Employee
9,933 Views
Registered: ‎01-03-2008

Re: risc processor design

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I took the code that you posted and ran it through XST and it generated 116 WARNINGS including important ones like these:

 

 

WARNING:HDLCompiler:413 - "src/final_add3.v" Line 672: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "src/final_add3.v" Line 673: Result of 32-bit expression is truncated to fit in 8-bit target.

WARNING:HDLCompiler:91 - "src/final_add3.v" Line 209: Signal <PCount> missing in the sensitivity list 

WARNING:Xst:737 - Found 1-bit latch for signal <Exe<6>>. Latches may be generated from incomplete case or if statements
WARNING:Xst:737 - Found 1-bit latch for signal <Exe<5>>. Latches may be generated from incomplete case or if statements
WARNING:Xst:737 - Found 1-bit latch for signal <Exe<4>>. Latches may be generated from incomplete case or if statements

WARNING:Xst:2042 - Unit bips1: 8 internal tristates are replaced by logic (pull-up yes): BusWires<0>, BusWires<1>, BusW
ires<2>, BusWires<3>, BusWires<4>, BusWires<5>, BusWires<6>, BusWires<7>.
WARNING:Xst:2042 - Unit dec2to4: 4 internal tristates are replaced by logic (pull-up yes): Y<0>, Y<1>, Y<2>, Y<3>

 Start by cleaning up your code first and removing most if not all of the WARNINGs (there may be a couple that can't be removed).

 

Start first with the latches that were generated and then the size mismatches.

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post