I am currently running the Axi Stream DMA example with interrupts and scatter gather. xaxidma_example_sg_intr.c, found with the 18.2 SDK. My board is the ZCU102
My vivado block design is just the cpu hooked up to the DMA with an AXI fifo acting as the loopback peripheral (essentially data goes out to the DMA, straight to a FIFO, and out the FIFO back to the CPU).
The example code works great. However, I am trying to modify it to send packets larger than 8 bits and am a bit lost.
My modified code is attached, and so far the first 4 transmissions ( 32 bit 0xC,0xD,0xE and 0xF) pass, but 0x10 fails. The error message is
Data error 4: 1F1E1D1C/10
I adjusted all of the sizes to 32 bits and not 8 bits, but clearly I am having some C memory issues.
Also, in general I am confused about Buffer Descriptors, packets, transmissions, etc.
I am guessing something is up with the following Macros as changing them seems to change behavior, but I am at a loss for what they do
#define MAX_PKT_LEN 0x8
#define MARK_UNCACHEABLE 0x701
* Number of BDs in the transfer example
* We show how to submit multiple BDs for one transmit.
* The receive side gets one completion per transfer.
#define NUMBER_OF_BDS_PER_PKT 2
#define NUMBER_OF_PKTS_TO_TRANSFER 1
#define NUMBER_OF_BDS_TO_TRANSFER (NUMBER_OF_PKTS_TO_TRANSFER * \
What is a packet?
What is a buffer descriptor?
Why are multiple buffer descriptors sent during one packet? Why shouldn't you just send one large BD with the entire message?