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Visitor
Visitor
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Registered: ‎04-06-2011

spartan 3a dsp constraints error

Hi
I have problem with bitstream generation when I add  code to .ucf file. I get error :

 

ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
   Conflicting IO Standards are:
   IO Standard 1: Name = LVCMOS33, VREF = NR, VCCO = 3.3, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = 2
   List of locked IOB's:
       LCD_IO_pin<0>
       LCD_IO_pin<1>
       LCD_IO_pin<2>
       LCD_IO_pin<3>
       LCD_IO_pin<4>
       LCD_IO_pin<5>
       LCD_IO_pin<6>

 

added code is:

 

#### Module LCD_IO constraints

# LCD_FPGA_DB4
Net LCD_IO_pin<6> LOC = G21;
Net LCD_IO_pin<6> IOSTANDARD=LVCMOS33;
Net LCD_IO_pin<6> PULLDOWN;
Net LCD_IO_pin<6> SLEW=SLOW;
Net LCD_IO_pin<6> DRIVE=2;
# LCD_FPGA_DB5
Net LCD_IO_pin<5> LOC = R19;
Net LCD_IO_pin<5> IOSTANDARD=LVCMOS33;
Net LCD_IO_pin<5> PULLDOWN;
Net LCD_IO_pin<5> SLEW=SLOW;
Net LCD_IO_pin<5> DRIVE=2;
# LCD_FPGA_DB6
Net LCD_IO_pin<4> LOC = D25;
Net LCD_IO_pin<4> IOSTANDARD=LVCMOS33;
Net LCD_IO_pin<4> PULLDOWN;
Net LCD_IO_pin<4> SLEW=SLOW;
Net LCD_IO_pin<4> DRIVE=2;
# LCD_FPGA_DB7
Net LCD_IO_pin<3> LOC = D24;
Net LCD_IO_pin<3> IOSTANDARD=LVCMOS33;
Net LCD_IO_pin<3> PULLDOWN;
Net LCD_IO_pin<3> SLEW=SLOW;
Net LCD_IO_pin<3> DRIVE=2;
# LCD_FPGA_RW
Net LCD_IO_pin<2> LOC = J19;
Net LCD_IO_pin<2> IOSTANDARD=LVCMOS33;
Net LCD_IO_pin<2> PULLDOWN;
Net LCD_IO_pin<2> SLEW=SLOW;
Net LCD_IO_pin<2> DRIVE=2;
# LCD_FPGA_RS
Net LCD_IO_pin<1> LOC = H20;
Net LCD_IO_pin<1> IOSTANDARD=LVCMOS33;
Net LCD_IO_pin<1> PULLDOWN;
Net LCD_IO_pin<1> SLEW=SLOW;
Net LCD_IO_pin<1> DRIVE=2;
# LCD_FPGA_E
Net LCD_IO_pin<0> LOC = J20;
Net LCD_IO_pin<0> IOSTANDARD=LVCMOS33;
Net LCD_IO_pin<0> PULLDOWN;
Net LCD_IO_pin<0> SLEW=SLOW;
Net LCD_IO_pin<0> DRIVE=2;


I am using edk 11.4 and XC3SD3400A-4FGG676C fpga. I seen this answer http://www.xilinx.com/support/answers/33927.htm but it doesnt help me at all because I dont understand what I need to change. Full content of .ucf file is in attachment. Maybe someone can help me with this

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Anonymous
Not applicable
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Please refer http://www.xilinx.com/support/answers/25159.htm related to your issue
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