11-07-2011 02:48 AM
hello at everybody
I'm trying to start to do some test with a Xilinx ML605 Evaluation
Board, making use of a FPGA Virtex 6 core.
I would map a very simple algorithm to fpga at the beginning (like a
counter for example), but I have some communication problems with the
board. I don't know what port I can use and how to estabilish the
Can you help me with some simple examples?
thank you all
11-07-2011 02:57 AM
11-07-2011 03:20 AM
Thank you very much.
I have done the verification of the board's functionality as reported in "Getting Started with the
Xilinx Virtex-6 FPGA ML605 Evaluation Kit" (pag 1 to 27) but I didn't test the board by PCI Express because I have a laptop. Now I would know if I can map and synthetize a simple project by the JTAG Cable Connector. Have I install some driver or somthing like that to estabilish the connection?
I've used a spartan 3a fpga and I had not problem to synthetize and map a simple project with the usb cable and the ISE design tool but with this board I don't succed.
Thanks a lot for the replay.
11-07-2011 09:20 AM
11-07-2011 10:16 AM
Thank you very much...
I was using this port (see the picture) with the usb cable. The ISE version is 12.4
I will try to follow the guide you indicate.
See you soon
11-08-2011 01:31 AM
I've read the guide and I nocticed I didn't use the cable (xilinx platform cable usb see the figure I attached) indicated in the guide.
Instead I used the jtag usb port and the cable indicated in the figure above (previous post).
What have I do?
Thanks a lot.