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Contributor
Contributor
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Registered: ‎10-24-2013

ten_gig_eth_mac_axi ip core support for KC705 Connectivity Kit

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Hi,

 

I have just bought Kintex 7 based Connectivity Kit KC705 and trying out the user guide mentioned routine Rebuilding the design (from UG927 v4.0). I have installed Vivado 2013.2 and running it with the device locked node locked license (Kintex 7 Connectivity Kit Embedded Edition) that came with the kit. The board design I am using is the k7_connectivity_trd_v1_5. 

 

During the synthesis run I have got the error message that Ten Gigabit Ethernet MAC AXI4 core is not found. Do I need to purchase the core just to try out rebuilding the design or the issue is somewhere else? Also where can I find the pre generated bit file for the same so that I can atleast check the functionality of the device?

 

The error messages are as follows:

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ERROR: [Synth 8-439] module 'ten_gig_eth_mac_axi_st_ip' not found [C:/Users/nilkund/KC705/k7-connectivity-trd/k7_connectivity_trd_v1_5/design/source/network_path/network_path.v:218]

ERROR: [Synth 8-285] failed synthesizing module 'network_path' [C:/Users/nilkund/KC705/k7-connectivity-trd/k7_connectivity_trd_v1_5/design/source/network_path/network_path.v:44]
ERROR: [Synth 8-285] failed synthesizing module 'k7_connectivity_trd' [C:/Users/nilkund/KC705/k7-connectivity-trd/k7_connectivity_trd_v1_5/design/source/k7_connectivity_trd.v:63]

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Thanks & Regards,

Prashant

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2007

Prashant, Anton,

 

Vivado is shipped witha license file that contains many Design_Linking licenses, which should allow you to synthesize a design containing the IP core.  However, in Vivado 2013.2, the Design_Linking licenses are not being recognized.  Please see (Xilinx Answer 56696) for details.  This has been resolved in Vivado 2013.3, but as you are running the 2013.2 TRDs you need to stick with 2013.2 software.  For that reason, the workaround included in (Xilinx Answer 56696) should help you here.

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Contributor
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Registered: ‎10-24-2013

I tried the version 1.3 of same TRD and it shows missing modules- PCIE external clock source and PCIE x8gen2 core top module. Does Xilinx recheck the synthesis of TRDs before making them available to the end users? The errors are listed below. The system is the same as mentioned yesterday.

 

ERROR: [Synth 8-439] module 'pcie_x8gen2_axi_st_ip_pipe_clock' not found [C:/Users/nilkund/KC705/k7_connectivity_trd_v1_3/k7_connectivity_trd_v1_3/design/source/k7_connectivity_trd.v:601]

ERROR: [Synth 8-285] failed synthesizing module 'k7_connectivity_trd' [C:/Users/nilkund/KC705/k7_connectivity_trd_v1_3/k7_connectivity_trd_v1_3/design/source/k7_connectivity_trd.v:61]

 

Waiting for a reply from Xilinx support staff.

 

Thanks. 

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Visitor
Visitor
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Registered: ‎09-25-2013

Hello, prashant.nilkund!

Have you solved your problem? I have very similar problem with VC709.

1. If I run synthesis with Vivado 2013.2:

cores 'ten_gig_eth_mac_axi_st_ip' and ''ten_gig_eth_pcs_pma_ip" are locked due to absence of license.

 

"[Designutils 20-1365] Unable to generate target(s) for the following file is locked: c:/Anton/v7_xt_conn_trd/vivado/project_1/xt_connectivity_trd.srcs/sources_1/ip/ten_gig_eth_mac_axi_st_ip/ten_gig_eth_mac_axi_st_ip.xci
Locked reason: IP 'ten_gig_eth_mac_axi_st_ip' requires a license but no valid license was found. No useable outputs are available for this IP. However license checkpoints may prevent use of this IP in some tool flows. Please select 'Report IP Status' from the 'Tools' menu for instructions to unlock.".
 
and
 
"[Designutils 20-1365] Unable to generate target(s) for the following file is locked: c:/Anton/v7_xt_conn_trd/vivado/project_1/xt_connectivity_trd.srcs/sources_1/ip/ten_gig_eth_pcs_pma_ip/ten_gig_eth_pcs_pma_ip.xci
Locked reason: IP 'ten_gig_eth_pcs_pma_ip' requires a license but no valid license was found. No useable outputs are available for this IP. However license checkpoints may prevent use of this IP in some tool flows. Please select 'Report IP Status' from the 'Tools' menu for instructions to unlock.
 
2. If I use 2013.3, then several source files cannot be found (top and clock like in your case). I found the files with similar names in example project generated for PCIe IP core and copied them to TRD design. But many other errors appeared due to incompatibility of TRD 2013.2 with Vivado 2013.3.

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2007

Prashant, Anton,

 

Vivado is shipped witha license file that contains many Design_Linking licenses, which should allow you to synthesize a design containing the IP core.  However, in Vivado 2013.2, the Design_Linking licenses are not being recognized.  Please see (Xilinx Answer 56696) for details.  This has been resolved in Vivado 2013.3, but as you are running the 2013.2 TRDs you need to stick with 2013.2 software.  For that reason, the workaround included in (Xilinx Answer 56696) should help you here.

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Contributor
Contributor
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Registered: ‎10-24-2013

I upgraded my vivado edition to 2013.4 and now it works. Otherwise you need to ask for the license file for the particular IP from xilinx.

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