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6,885 Views
Registered: ‎10-12-2009

vc707 ddr3 interface issue

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Hello,

 

I am using Vc707 board, 14.5 ISE DS.

During the development of XPS project I encountered the problem with ddr3 memory interface.

In my XPS design (based on referent vc707 BIST project available on Xilinx website) software (uses DDR3) sometimes behaved unexpectedly. To verify memory interface I developed a very simple DDR3 memory write/read test app and put it into BRAM. The app proved that there is a DDR3 memory interface issue as read data in some cases didn't matched the written data. When happened, the error was always on the same bit and always on 0 to 1 transition: instead of written 0xFF app sometimes reads 0xFD.

Memory test (which is part of referent vc707 BIST) ends with no error indicated. My test app on original vc707 BIST HW gives the same result ( with occasional wrong read data).

I also tried to create new XPS project using BSB wizard for vc707 platform. With default parameters, the result was DDR3 interface that run on 400MHz - half of the one on referent project . Anyways, the problem with DDR3 interface remained.

In all cases implementation finished with timing score 0.

Is possible that we have some kind of hardware issue (PCB design issue, cold solder?). We have only one vc707 board, so we can't  compare. It would be great if anyone can run our test SW on some other vc707. This will definitely help to track down the issue.

The app is extended hello world example, with buffer placed in DDR3. heloworld.c and lscript.ld are attached.

 

Thanks in advance

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10,990 Views
Registered: ‎10-12-2009

Re: vc707 ddr3 interface issue

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Thanks Athandr,

I didn’t try running MIG design.

In my design MB was only master on AXI interconnect, and DDR3 only slave. 

Later, when (freeze current problem and continue with others features), I add my custom peripheral (as another master on AXI Interconnect), 

and problem disappeared. Very strange. This is definitely some issue with AXI Interconnect.

 

Best Regards,

Dragan

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Xilinx Employee
Xilinx Employee
6,816 Views
Registered: ‎07-31-2012

Re: vc707 ddr3 interface issue

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Hi,

 

Did you try running the MIG design in the VC707 page on Xilinx.com. in case you haven't tried check the below links. Try running this design and check if you are still receiving the wrong data.

 

1) PDF - LINK

2) Design - link

 

Other VC707 docuementation can be found from the link - link.

 

Thanks,

 

 

Thanks,
Anirudh

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10,991 Views
Registered: ‎10-12-2009

Re: vc707 ddr3 interface issue

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Thanks Athandr,

I didn’t try running MIG design.

In my design MB was only master on AXI interconnect, and DDR3 only slave. 

Later, when (freeze current problem and continue with others features), I add my custom peripheral (as another master on AXI Interconnect), 

and problem disappeared. Very strange. This is definitely some issue with AXI Interconnect.

 

Best Regards,

Dragan

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