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Visitor
Visitor
19,132 Views
Registered: ‎08-29-2011

verilog help with clock divider

Hi Everyone,

 

Sorry if this is a simple question but I'm struggling with this issue - I'm using a coolrunner II and thought I would try and learn verilog by converting the VHDL example in the handbook - The problem is that I can not get a clock divider to work. The issue is that I can see in ISim that clock_div_int is changing as expected but it never triggers the always loop and so clock_div remains "x".

 

module clock_divide(    input clock_osc,    output clock_div    );
reg [9:0] count;

wire clock_div_int;

count =10'b0;

 

CLK_DIV16 CLK_DIV16_inst ( .CLKDV(clock_div_int),  .CLKIN(clock_osc));      

always @(posedge clock_div_int) begin

count <= count + 1;

end

 

assign clock_div = count[9];

endmodule

 

Many thanks

 

Ross

 

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6 Replies
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Scholar
Scholar
19,128 Views
Registered: ‎02-27-2008

Re: verilog help with clock divider

Ross,

Don't you want to do something on the input clock? You have "always @(posedge clock_div_int)" which I thought was your output?

Where do you change the state of your output?
Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
19,127 Views
Registered: ‎07-21-2009

Re: verilog help with clock divider

Are error messages generated when synthesising your design?

 

Couldn't find a 'handbook', perhaps you could post a link, or (better) post the original VHDL code.

 

You're new to Verilog design, right?

 

Here's a quick example of a clock divider:

 

reg [3:0] count;  // clock divider counter

reg       clk_div;  // clock divider output

 

always @ (posedge clock_in)

  begin

    if (count==4'b1001)  // divide by 10

       count <= 4'b0000;  // reset to 0

    else count <= count+1;  // increment counter

    clk_div  <=  (count == 4'b0000);  // counter decoded, single cycle pulse is generated

  end

 

-- Bob Elkind

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Highlighted
Visitor
Visitor
19,123 Views
Registered: ‎08-29-2011

Re: verilog help with clock divider

So I found the solution - Thanks everyone - Very very simple mistake.

 

I screwed up the initilization of the count - I needed to:

 

initial

    count = 0;

 

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Visitor
Visitor
19,120 Views
Registered: ‎08-29-2011

Re: verilog help with clock divider

Hi I made a really silly error. Apologies - I'm only a few hours into learning verilog - forgot to initialize count.  For those interested the handbook I'm refering too is the handbook that comes with the coolrunner-II CLPD starter kit.

 

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Professor
Professor
19,111 Views
Registered: ‎08-14-2007

Re: verilog help with clock divider

module clock_divide(    input clock_osc,    output clock_div    );
reg [9:0] count = 0;

wire clock_div_int;

// count =10'b0; This assignment is not within a process block (wasn't there an error?)

 

CLK_DIV16 CLK_DIV16_inst ( .CLKDV(clock_div_int),  .CLKIN(clock_osc));      

always @(posedge clock_div_int) begin

count <= count + 1;

end

 

assign clock_div = count[9];

endmodule

This should help (simulation will not "increment" an 'X' value.  You need to start from a known value like zero)

However if you have synthesized the code I expect it would have worked...

 

-- Gabor

 

Edit:

 

Just saw that you beat me to the post  :-)

Maybe next time you'll work a little longer before asking the easy questions...

 

My method is equivalent to the "initial" statement.  You could also have introduced a reset

signal to accomplish the initialization.

-- Gabor
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Newbie
Newbie
7,564 Views
Registered: ‎05-10-2016

Re: verilog help with clock divider

Hi

this is not a clock divder. Actually it's a clock multiplier or, say, frequency divider.

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