xapp1305 (10G_PL) Write Bitstream Error

[legendbb]

2016.4 trying to rebuild bitstream, but failed with this message:

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
pl_eth_10g_i/xxv_ethernet_0/inst/i_pl_eth_10g_xxv_ethernet_0_0_top_0/i_pl_eth_10g_xxv_ethernet_0_0_CORE (pl_eth_10g_xxv_ethernet_0_0_xxv_ethernet_v2_0_1_mac_baser_axis_hsec_cores)

I have Design_Linking IP license available.

Any hints?

Thanks,

[vijayak]

Hi @legendbb

A Simulation-Only or Design-Linking license for a LogiCORE IP Core is an evaluation license key that allows you to run through the entire design flow and perform both pre- and post-implementation simulation. However, you cannot generate bitstreams for designs that contain LogiCORE IP Cores enabled by a Simulation Only license.

[yenigal · Accepted solution]

Hi

You can use the evaluate option from below link to generate the Hardware Evaluation license so that you can generate a time limited bit file for the xapp and test it on your board.

https://www.xilinx.com/products/intellectual-property/ef-di-25gemac.html