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Observer goer001
Observer
315 Views
Registered: ‎10-09-2019

*.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

I own an Digilent Avnet Zedboard (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D). This is an older version of the zedboard. Can anyone upload the master *.XDC file for this specific board? I looked at the master *.XDC files available at this website and I believe that it is incompatible with my specific development kit. Is Silica Avnet, Xilinx, or Digilent, supposed to make this file available to the public. I checked the website, GitHub, however, it appears that the file is missing.

The correct file should match, (or be very similar to), the file made reference to on page 34 of the Silica Avnet Vivado tutorial that I have attached.

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8 Replies
Moderator
Moderator
255 Views
Registered: ‎11-09-2015

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

Hi @goer001 

The xdc file can be download for the zedboard website (http://zedboard.org/support/documentation/1521):

zed.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Observer goer001
Observer
219 Views
Registered: ‎10-09-2019

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

Dear Sir:

     My apologies for the belated reply.  I transgressed from the solution that you had pointed me to.   Since I am using Vivado, I downloaded the *.XDC file (not the *.UCF file) and attempted to complete the tutorial that I had uploaded at this website.    If you go to page 34 of the tutorial and compare the *.XDC file found on that page to the *.XDC file found on the download link that you had pointed me to - you will see that the *.XDC  code differs.  The tutorial that I had uploaded may be using terms associated with *.TCL scripts (see page 34 of the uploaded tutorial).  I created a .XDC file by converting from what I believe may be *.TCL associated scripts to the *.XDC format that was downloaded from the website that you had pointed me to.   There was a problem.   I did not know how to convert last 2 snippets of code (found on page 34 of the tutorial I uploaded) to *.XDC file format that you had pointed me to so I copied and pasted those 2 code snippets into my *.XDC file.  When I ran the lab tutorial that I had uploaded - 2 error messages were generated during the "generate bitstream" phase.    I believe that the 2 code snippets that I opied and pasted into the *.XDC file are the source of the error. 

      I have attached is a screenshot of the 2 error messages: 

      If you look at the last 2 lines of code on page 34 of the tutorial.   This code that is probably generating the error message is:


set_property PULLDOWN true [get_ports {spi_0_*}]
set_property PULLDOWN true [get_ports {gpio_rtl_tri_io[*]}]

       Can you tell me how to convert this code into the *.XDC format in a generalized manner?

       In other words, how do I identify what "gpio_rtl_tri_io[*]" and "spi_0_*" does exactly in my program starting from these 2 code snippets.   In other words, given 2 arbitrary code snippets, how would you reference these 2 code snippets to a Vivado manual (working backwards)? 

        I believe that these 2 code snippet "initialize" a program task and I may require a second reference that will explain what these 2 code snippets do with regard to getting this particular program to run correctly.

        Therefore, I believe that I need 2 explanations:

1)  A generalized method that explains code conversion to a *.XDC file format working from 2 arbitrary code snippets. 

2)  An explanation of how these 2 code snippets facilitate the working of this particular program.   In other words, can you write out in long form (if possible) what the * operator will output, in terms of all the lines of code generated, for both code snippets, and how do these lines of code facilitate the operation of the required tasks to get this particular function to operate correctly in the GPIO module. 

 I need to convert these 2 code snippets into compatible *.XDC lines of code.

 I will upload the complete tutorial if you may require further explanation of how this particular exercise operates.  

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Moderator
Moderator
193 Views
Registered: ‎11-09-2015

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

HI @goer001 

You are missing the following constraints which are mentioned in the tutorial:

set_property PACKAGE_PIN AA11 [get_ports spi_0_io0_io]
set_property PACKAGE_PIN Y10 [get_ports spi_0_io1_io]
set_property PACKAGE_PIN AA9 [get_ports spi_0_sck_io]
set_property PACKAGE_PIN Y11 [get_ports {spi_0_ss_io[0]}]
set_property PACKAGE_PIN F22 [get_ports {gpio_rtl_tri_io[0]}]
set_property PACKAGE_PIN G22 [get_ports {gpio_rtl_tri_io[1]}]
set_property PACKAGE_PIN H22 [get_ports {gpio_rtl_tri_io[2]}]
set_property PACKAGE_PIN F21 [get_ports {gpio_rtl_tri_io[3]}]
set_property PACKAGE_PIN H19 [get_ports {gpio_rtl_tri_io[4]}]
set_property PACKAGE_PIN H18 [get_ports {gpio_rtl_tri_io[5]}]
set_property PACKAGE_PIN H17 [get_ports {gpio_rtl_tri_io[6]}]
set_property PACKAGE_PIN M15 [get_ports {gpio_rtl_tri_io[7]}]
set_property PACKAGE_PIN T22 [get_ports {gpio_rtl_tri_io[8]}]
set_property PACKAGE_PIN T21 [get_ports {gpio_rtl_tri_io[9]}]
set_property PACKAGE_PIN U22 [get_ports {gpio_rtl_tri_io[10]}]
set_property PACKAGE_PIN U21 [get_ports {gpio_rtl_tri_io[11]}]
set_property PACKAGE_PIN V22 [get_ports {gpio_rtl_tri_io[12]}]
set_property PACKAGE_PIN W22 [get_ports {gpio_rtl_tri_io[13]}]
set_property PACKAGE_PIN U19 [get_ports {gpio_rtl_tri_io[14]}]
set_property PACKAGE_PIN U14 [get_ports {gpio_rtl_tri_io[15]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spi_0_*}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpio_rtl_tri_io[*]}]

 

This is why you are getting the error


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Observer goer001
Observer
182 Views
Registered: ‎10-09-2019

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

Dear Sir:

     I would like to thank you for your reply.    

     I will make the attempt to utilize the code that was provided by you and I will get back to you with regard to your proposed remedy.   

      As I stated before, the *.XDC file that you linked me to is not the same as the code that you had posted.      It is my understanding that there is more than one method of creating an *.XDC file.    Therefore, I am under the belief that the code you posted can be referenced to a manual published by Xilinx corp. or third party vendor.

       Can you reference the code that you posted above to the appropriate reference manual and provide me a link to the reference manual?    

 

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Moderator
Moderator
164 Views
Registered: ‎11-09-2015

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

HI @goer001 

The part of the xdc I shared in part of the tutorial you attached to the topic... You should read carefuly while doing the tutorial...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer goer001
Observer
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Registered: ‎10-09-2019

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

The scope of my interests was broad.   If you felt that I had overlooked something, then please let me know what you believe I had overlooked.     If the matter concerns a topic that requires a more detailed explanation then please link me to a xilinx manual, or other tutorial.   

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Moderator
Moderator
128 Views
Registered: ‎11-09-2015

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

Hi @goer001 

If you want to learn about constraints, refer to UG903

But you shouldn't require this just to follow the tutorial


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer goer001
Observer
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Registered: ‎10-09-2019

Re: *.xdc file, Zynq 7000 Epp, 7Z020 CLG 484-1 Zedboard upload

I have made some progress on my own with regard to creating a *.xdc file that does not generate errors.

The purpose of this post was to create a working system for every application that my zedboard is capable of.   The tutorial that I uploaded was intended to be a only a guide - a stepping stone - to further this endeavor.

Following the tutorial did bring to light some problems that I would run into down the road. When I downloaded the *.xdc file from the link that you had pointed me to, I noticed that the *.xdc file in the tutorial was not the same as the *.xdc file that I had downloaded. This represents a very serious impediment for future development with this development board.

After reading the revision notes *.xdc file that I had downloaded from the link that you had pointed me, I am under the impression that I may require an old *.xdc file from the year 2013. It would be appreciated if you could provide me with the *.xdc file that was used during the year 2013. Uploading this file would be appreciated. If you cannot upload the file then I will have to create my own and, consequently, this will result in far more detailed questions that I will pose in future posts.

With regard to getting the tutorial *.xdc file to work, the cruix of the problem is that the "port names" that are used in the tutorial are not the same port names that are generated by the Vivado IDE that I am using (I am using Vivado 2013.4). When I modified the *.xdc file to reflect the port names generated by my Vivado IDE, all my error messages went away - with the exception of 1.

Although this is probably not the source of the error message that I am currently receiving, I do need to know the answer to this question. In the tutorial, the author claims there existed a software "bug" and the only remedy for it is to make a change to a buffer located in the wrapper. I would like to know what happens if this change is not made? Could the board successfully generate a bitstream even if the change was not made? If the answer to that question is yes, what functional error was observed in the board's operation?

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