I am trying to make a QAM processor with SystemGenerator for Simulink. At the moment, I drive an external clock into the virtex 2 FPGA who clocks the DACs and ADCs and routes the clock to the user FPGA. The design is quite simple, so the highest frequency achievable in the Virtex4 design (around 350 MHz,Timing Analysis) is enough for what I am trying to get.
When I try the design, the highest frequency I can drive the DACs with is around 115 MHz. The DAC datasheet says that it is possible to use a clock up to 160 MHz, and the data being driven to the DACs is oversampled before by 4 (i.e, data going to the DACs at ~29 MSPS, far from the capabilities of the DAC). If I try to use a faster clock, spikes/overvoltages appear in some of the level transitions. I've read as well that the DAC itself takes care of the unsynchronization of the data driven into it, so the output would be OK, but it's not my case. What could be the reason? any solution? I've been recommended to start using VHDL to have more control over the clock, but I want to listen to other ideas before changing the whole design to VHDL (and learn how to do it, of course)