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Participant sschekall
Participant
8,776 Views
Registered: ‎10-27-2013

zc702 ddr schematic issue

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I'm working on a new design and I'm using the zc702 design as a reference.

 

according to xtp185-zc702-schematic-ref1-1.pdf : Page9, Page16,17,18,19

 

xc7xz020clg484 pin D1  is DDR3_DQ0  : But it is  connected to U66.DDR3_DQ3

 

There are many other DQ pins that are connected strangely.

 

Is this a design problem?  Or is it something else happening here.?

Why are the DQ[31:0]  signals connected as they are?

Why not connect FPGA.DQ[7:0]  to DDR3.DQ[7:0]?

 

 

I checked "The Official Pinout" xc7z020clg484-pkg.txt  Can I trust this?

 

         

               Stan Schekall

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1 Solution

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Xilinx Employee
Xilinx Employee
15,424 Views
Registered: ‎07-11-2011

Re: zc702 ddr schematic issue

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Hi,

 

As per JEDEC DDR3 and MIG specifications DQ signals can be swapped with in teh byte lanes.

This is allowed and will not create any issues, this is just done for routing feasibility and better SI.

Please refer UG586 design guideliness DRR3  section for 7 series on placement rules

You can trust the pinout given in the site and go ahead safely, but the DQ routing on your board need not necessarily  go for swapping unless your board physics demand,  which will be known to the board deisgners

 

For more views on pin swapping please refer related topic below

 

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/DDRx-Layout-MIG-pin-swapping-and-Time-Delay/td-p/162006

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Spartan-6-DDR2-Swapping-data-pins/td-p/133472

 

 

Hope this helps

 

Regards,

Vanitha.

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2 Replies
Xilinx Employee
Xilinx Employee
15,425 Views
Registered: ‎07-11-2011

Re: zc702 ddr schematic issue

Jump to solution

Hi,

 

As per JEDEC DDR3 and MIG specifications DQ signals can be swapped with in teh byte lanes.

This is allowed and will not create any issues, this is just done for routing feasibility and better SI.

Please refer UG586 design guideliness DRR3  section for 7 series on placement rules

You can trust the pinout given in the site and go ahead safely, but the DQ routing on your board need not necessarily  go for swapping unless your board physics demand,  which will be known to the board deisgners

 

For more views on pin swapping please refer related topic below

 

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/DDRx-Layout-MIG-pin-swapping-and-Time-Delay/td-p/162006

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Spartan-6-DDR2-Swapping-data-pins/td-p/133472

 

 

Hope this helps

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
Participant sschekall
Participant
8,768 Views
Registered: ‎10-27-2013

Re: zc702 ddr schematic issue

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Thanks for the prompt, quality answer
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