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Anonymous
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zc702 - when is PL powered on?

Does the main power switch (SW11) also power on the PL?

 

I ask because in my FSBL when I read the DEVCFG Miscellaneous Control register, the PCFG_POR_B bit is set to 0, and based on the TRM, it states that this bit indicated the PL power status.

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Scholar
Scholar
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Registered: ‎02-27-2008

yes,

 

Power is applied to the Vdd pins for both the PS and PL.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
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In the SDK generated FSBL, it does a register dump after it initiates the DMA transfer. According to the Zynq TRM, it states bit 8 of the PCAP/DEVCFG Miscellaneous Status Register should be set, indicating that the PL is powered on. The read of this register currently returns all 0's.

 

Does that mean the PL isn't powered on at this point? 

 

register_dump.png

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Visitor
Visitor
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Registered: ‎02-06-2012

I am also finding bit 8 stays 0. Is this correct?
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Anonymous
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I was able to power on my PL actually, despite the bits all being 0.

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