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mshin
Contributor
Contributor
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Registered: ‎02-14-2014

zcu102/unable to debug in a standalone project/final goal is UDB data transfer (how to?)

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Hello all experts and Xilinx users,

I have a ZCU102 board. I want to send stream of data via UDP port to the PC.

1.First of all, because I am new to ZYNQs especially ultrascale+ series, to do an example I began to create a simple project which contains a GPIO at EMIO port and I put ILA and VIO to test input and outputs.

when I want to put it in debug mode, the debug curser didnt point to the first of main function, instead it went to endless unknown place when I put the pause button then a file named asp_vectors.S appeared and the debugger stoped at a place in that strange file. what's wrong with this setup which I could not debug the project correctly?

I have good experience in microblaze standalone project, I dont know the way I should work with ZYNQs are completely similar or not.

2.Finally I want to use the built in example using lwip library for sending stream of data to the pc as a server. is that example the right choice for this purpose?

 

best regards,

Meysam Sh.

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mshin
Contributor
Contributor
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Registered: ‎02-14-2014

I have used the modified fsbl file which provided here AR# 72113.

but it did not work. however exactly modifing DDR configuration manually as bellow fixed the problem.

Capture.PNG

neither AR# 72113 nor vivado 2019.1 help this.

please kindly  modify them and provide clear explaination.

 

 

Thanks and Regards

Meysam Sh.

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mshin
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Registered: ‎02-14-2014

my board is 0432055-05 and I replace the new fsbl from AR# 72113.

I use vivado 2018.3, but using vivado 2019.1 not help this issue.

Capture.PNG    this is DDR configuration:Capture.PNG

and this is boardUI.exe result:

Capture.PNG

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andresb
Xilinx Employee
Xilinx Employee
702 Views
Registered: ‎06-21-2018

Hi mshin,

Are you connecting your ZCU102 with a straight Ethernet cable to your PC's port?

What IP are you setting that port to?

Have you tried just pinging the ZCU102 from the Command window?

Thanks,
Andres

 

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nmanitri
Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018

Hello @mshin,

I use vivado 2018.3, but using vivado 2019.1 not help this issue.

I believe that in Vivado 2018.3, you have modified the FSBL file and it works for you while in Vivado 2019.1 you are facing the same issue. If this is the case, Have you run the "Hello World Example design" for Vivado 2019.1? Is it passing? If no, you need to modify the DDR Configuration setting and then run the  "Hello World Example design". For DDR Configuration settings please refer below link:

https://forums.xilinx.com/t5/Evaluation-Boards/ZCU102-Board-User-Interface-test-failed/m-p/989701#M22923

Regards,

Naveen 

 

 

 

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mshin
Contributor
Contributor
666 Views
Registered: ‎02-14-2014

I have used the modified fsbl file which provided here AR# 72113.

but it did not work. however exactly modifing DDR configuration manually as bellow fixed the problem.

Capture.PNG

neither AR# 72113 nor vivado 2019.1 help this.

please kindly  modify them and provide clear explaination.

 

 

Thanks and Regards

Meysam Sh.

View solution in original post

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