cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
tsengcode
Observer
Observer
338 Views
Registered: ‎08-29-2018

对native fifo操作写入数据后 的almost_empty、empty、almost_full、full信号为什么是不定值?

ZYNQ_MPSOC系列FPGA

tsengcode_0-1599013165572.png

 

tsengcode_0-1599012738919.png

 

0 Kudos
1 Reply
tsengcode
Observer
Observer
312 Views
Registered: ‎08-29-2018

 

原因找到了,rd_en和dout悬空就会出现这样的现象

tsengcode_0-1599019127296.png

 

0 Kudos