Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎09-28-2020

1G/2.5G Ethernet PCS/PMA or SGMII v16.0 - Deviating from the Reference Clocking Scheme

Hi there,

I'm working on a project to implement 1G SGMII on an Artix-7 device. The design is based on the 'Synchronous SGMII over LVDS' example design but in this case, due to cost constraints, the GTP reference clock is not being sourced from a 125MHz oscillator as per the example but instead from a 625MHz SGMII clock output from the PHY (a Texas Instruments DP83867IS). The PLL divider parameters in the A7GTP wrapper common have been modified to account for the change in the input clock frequency. The TI datasheet states that the clock source is continuous and 625MHz is within the frequency range stated in DS181.

To further complicate matters, the GTP quad is being shared, to support an HD-SDI interface. As far as I can see from the datasheet, this seems to be viable as the clocking between the two interfaces is completely separate although I've noted from previous forum posts that this use case falls into the 'advanced' category.

First question - If the 625MHz clock was being sourced from a suitable oscillator presumably this approach is workable? 

Second question - As the 625MHz clock is actually being sourced from the PHY, are there any potential issues here? Does anyone have any experience of this or a similar arrangement?

Many thanks,

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎05-01-2013

If you select 'Synchronous SGMII over LVDS', it means that SGMII IP core use SelectIO instead of any GT.

If you want to use GTP, you should select “Transceiver”

0 Kudos