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marc.pearson
Adventurer
Adventurer
8,062 Views
Registered: ‎02-12-2015

AXI-4 Stream Data FIFO TLAST signal

Hello,

 

I've been trying to debug my system comprising of an axi peripheral, a stream fifo and an axi dma.

 

I noticed that the m_axis_tlast signal on my FIFO is always low.

 

I feed in data from a counter (axi peripheral) on an external clock, and then (hope to) read this data on the PS clock. My counter provides the tvalid signal while the counter is below a threshold and then asserts tlast and drops tvalid. After a period of time the cycle starts again.

 

I see the output data on the master FIFO signals as expected when I assert the m_axis_tready signal. The tvalid signal also looks good - just no tlast action!

 

I have experiemented with different FIFO depths but I never seem to get a tlast signal out, and I think I need this to drive my DMA properly.

 

Also, if anyone could explain the axis_data_count, wr_data_count and rd_data_count signals that would help as the values on these signals have confused me.

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3 Replies
rmanocha
Xilinx Employee
Xilinx Employee
500 Views
Registered: ‎11-22-2019

Hi marc.pearson,

 

I am also observing same behavior with AXI Stream FIFO m_axis_tlast signal. It doesn't pulse and DMA need this tlast for EOF signal. Let me know if you solved this issue.

 

Thanks

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derekm_
Voyager
Voyager
477 Views
Registered: ‎01-16-2019

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derekm_
Voyager
Voyager
396 Views
Registered: ‎01-16-2019

Yes, the XADC solution I posted above doesn't apply, I think.

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