03-06-2015 06:54 AM
I've been trying to debug my system comprising of an axi peripheral, a stream fifo and an axi dma.
I noticed that the m_axis_tlast signal on my FIFO is always low.
I feed in data from a counter (axi peripheral) on an external clock, and then (hope to) read this data on the PS clock. My counter provides the tvalid signal while the counter is below a threshold and then asserts tlast and drops tvalid. After a period of time the cycle starts again.
I see the output data on the master FIFO signals as expected when I assert the m_axis_tready signal. The tvalid signal also looks good - just no tlast action!
I have experiemented with different FIFO depths but I never seem to get a tlast signal out, and I think I need this to drive my DMA properly.
Also, if anyone could explain the axis_data_count, wr_data_count and rd_data_count signals that would help as the values on these signals have confused me.
12-08-2020 08:46 PM
I am also observing same behavior with AXI Stream FIFO m_axis_tlast signal. It doesn't pulse and DMA need this tlast for EOF signal. Let me know if you solved this issue.
12-09-2020 03:29 AM - edited 12-09-2020 03:29 AM
I think what you're looking for is contained in this blog post:
Also, a second solution by the same author here: