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svenssonjoel
Contributor
Contributor
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Registered: ‎03-17-2016

AXI_BRAM_CTRL + BLK_MEM_GEN Noob question (Vivado 2020.2)

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Hi,

 

I cannot make AXI_BRAM_CTRL to work with a BLK_MEM_GEN. (axi bram controller 4.1 and block memory generator 8.4).

connection.png

I feel like I have tried every possible setting in each of these IP and get nowhere. What I want to do to begin with should be simple (I feel), just set up a BRAM and AXI, then write some software for the arm core that reads and writes on the bram (to see that I can get it to run).

But I don't get anything that can be synthesized at all.

no_such_file.png

The picture above shows an error. The file that it claims is missing exists though and contains the following (which I feel is irrelevant and should not be there at all):

create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]

Since the bram should be getting its clock from the Axi bram ctrl module...

If this context is needed I use a Zynq7010.

Does anyone know of a step by step setup guide for this simple experiment. axi_bram_ctrl + blk_mem_gen in Vivado 2020?

If you directly see what kind of foolish noobishness I am up to, then please point me rightwards

 

Have a great day.

 

 

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svenssonjoel
Contributor
Contributor
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Registered: ‎03-17-2016

Ok! Now it is starting to make more sense;)

After a reboot, the problems come back. So it was about my environment and the fix is to do "export LC_NUMERIC=en_US.UTF-8".

So exporting that environment setting is the key, but the synthesis was still erroring-out and to fix that I had to reset all the "output products" (stuff Vivado generates). After that It synthesizes fine

Thanks!

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svenssonjoel
Contributor
Contributor
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Registered: ‎03-17-2016

Continuation on above (perhaps). I am not sure it is related.

I started a fresh project to just experiment with the BRAM and AXI CTRL for it. If I load this project I get the following errors:

loading_project.png

That does not sound very good. Don't know if it is in any way related to the problem in the first message in this thread though.

The design looks like this:

design.png

Trying to synthesize this "loaded up" project gives a slightly different error situation:

error.png

But I cannot help to think that all of this is somehow related.

This was just some additional information in case it helps someone know what the problem is.

 

Thanks and have a great day.

 

 

 

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@svenssonjoel 

I created the same design you provided from scratch in Vivado Design Suite 2020.2.

forums_zc706_axibramctrl.png

I was able to successfully implement.  I have attached the Vivado 2020.2 Project Archive if you want to test on your local machine.

If you still have errors, you might want to verify the Vivado Design Suite 2020.2 installation file digest to make sure you don't have a corrupt download/installation.  You can reference the Vivado Design Suite Release Notes, Installation, and Licensing User Guide (UG973; v2020.2). in Chapter 4: Download and Installation in section Verify the Digest.

forums_verify_digest_1.png

forums_verify_digest_2.png

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svenssonjoel
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Registered: ‎03-17-2016

Thanks,

I am so confused right now... This is the worst kind of problems.. The ones that just "magically" goes away.

I tried your project and it synthesizes fine. So then I loaded my bram_test project up and now that synthesizes fine as well! So then I create an entirely new project and create the same design again and that also synthesizes without problems.

I think I will give my computer a reboot and give it one more go.

Anyway, thanks for the help!

 

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svenssonjoel
Contributor
Contributor
501 Views
Registered: ‎03-17-2016

Ok! Now it is starting to make more sense;)

After a reboot, the problems come back. So it was about my environment and the fix is to do "export LC_NUMERIC=en_US.UTF-8".

So exporting that environment setting is the key, but the synthesis was still erroring-out and to fix that I had to reset all the "output products" (stuff Vivado generates). After that It synthesizes fine

Thanks!

View solution in original post

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@svenssonjoel 

Glad you were able to figure this out and thank you for posting to the Forums for the greater community knowledge.

It is nice to know what is happening rather than fear the unknown.

Please Reply, Kudos, and Accept as Solution.