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Observer
Observer
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Registered: ‎02-02-2012

AXI DMA S2MM on zynq with 32bit wide HP port gives saves only half the words,

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I got a loose end and i do not like that... mightbe one of you can explain it or give me a hint where to look further.

  1. Design description

On a zynq-7000 we use the AXI dma to get a AXI stream from the PL into the DDR memory connected to the PS. We use vivado 2017.2

Configuration is pretty standard as shown below: the axi dma is connected trough an intterconnect block to the processing system. Both SG as S2MM port are connected.

DMA_blockdesign.PNG

 

The AXI dma is configured to take in a 32bit AXI4S stream and push it on a 32bit AXIMM port out

DMA_IP_config.PNG

 

The HP0 port HAS to be configured to 64bit to make it work perferct. 

Zynq7_PS_HP0_setting.PNG

From SW point we use what comes out of petalinux together with the dma-proxy example, the only changes we did was strip out the TX channel.

It is outlined here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842418/Linux+DMA+From+User+Space

2 Experiment: We init a sw buffer to 0xdeadbeaf and pass it to the dma. We transfer a simple 32bit count from 1 to x we and readback the buffer:

With HP0 configured to be 64bit (good): 0x0000_0001,0x0000_0002,0x0000_0003, 0x0000_0004..

With HP0 configured to be 32bit (bad):  0x0000_0001,0xDEADBEAF,0x0000_0003, 0xDEAD_BEAF ..

3 Actual questioin: why does the design ommits half of the 32bit words if one changes the HP0 port config from 64bit to 32bit?

Notes: we noticed that the device tree (generated from the HDF file) does not change... there is a width parameter indicated there of the dma channel... but probably that points to the width setting of the dma access mm port and NOT the HP port?

2 ) Has anybody a working design with a 32bit width HP0 port?

3) Does anybody know where the S AXI HP0 DATA WIDTH setting gets reflected in sw? Mightbe in device tree or somewere else?

My feeling is there is a lowlevel bug in the Xilinx dma driver or in the hwdef generation... but i could be wrong of course.

 

Kr,

  Johannes Vanoverschelde

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Highlighted
Observer
Observer
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Registered: ‎02-02-2012

Found the rootcause:

The FSBL and the FPGA where out of sync. Configuring the HP0 port is done during first stage boot, AFI0 register set.

If one looks in the ps_init.html one finds

AFI_RDCHAN_CTRL@0XF8008000 and AFI_WRCHAN_CTRL@0XF8008014 where n32BitEn "Configures the Channel as a 32-bit interface. 1: 32-bit enabled 0: 64-bit enable"

The HWDEF followed the fpga code nicely. The reason the FSBL got out sync must be some missing build dependency in petalinux. A clean clone of the code and complete rebuild evenutally brought both again in sync. Long live CI :-).

Kr,

  Johannes

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Highlighted
Observer
Observer
769 Views
Registered: ‎02-02-2012

Found the rootcause:

The FSBL and the FPGA where out of sync. Configuring the HP0 port is done during first stage boot, AFI0 register set.

If one looks in the ps_init.html one finds

AFI_RDCHAN_CTRL@0XF8008000 and AFI_WRCHAN_CTRL@0XF8008014 where n32BitEn "Configures the Channel as a 32-bit interface. 1: 32-bit enabled 0: 64-bit enable"

The HWDEF followed the fpga code nicely. The reason the FSBL got out sync must be some missing build dependency in petalinux. A clean clone of the code and complete rebuild evenutally brought both again in sync. Long live CI :-).

Kr,

  Johannes

View solution in original post