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c.fauvel
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Registered: ‎01-12-2018

AXI_IIC Kintex 7 - Not alive ?

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Hello everybody,

I am facing an issue with an AXI_IIC block on a custom Kintex 7 board. I use a Microblaze on the FPGA, interfacing with a single device (uDAC from Analog Device). The Microblaze is interfaced to the AXI_IIC block via an AXI_Peripheral bridge and everything is clocked by a 100MHz clock. Everything looks good from the FPGA side (timing requirements successfull, ...).

 

I have checked the external pull up on the bus and the voltage and everything is fine. When I use a simple code, heavily inspired by the one found in this thread : https://forums.xilinx.com/t5/Embedded-Development-Tools/AXI-IIC-not-generating-stop-condition-throttles-scl-instead/td-p/789126, I am able to view a start condition ... and that's it.

No clock or data can be viewed on the SDA and SCL lines.

 

I tried to use the Active SDA option to "0" or to "1" but it doesn't change anything. 

Do you have any ideas ?

 

Best regards,

start_cond.png
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c.fauvel
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Registered: ‎01-12-2018

Hello everyone,

Finally, answering to myself :

I was able to have I2C frames by using this vhdl code instead of an IOBUF.

i2c_sda <= s_sda_out when s_sda_dir = '0' else 'Z';
s_sda_in <= i2c_sda;
i2c_scl <= s_scl_out when s_scl_dir = '0' else 'Z';
s_scl_in <= i2c_scl;

Best regards,

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c.fauvel
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Registered: ‎01-12-2018

Hello everyone,

I also add an ILA for the sda_[i,o,t] and scl[i, o, t] signals. The picture below show the idle state of the i2c bus, and also the top wrapper vhdl file.

Best regards,

 

ila.png
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c.fauvel
Visitor
Visitor
288 Views
Registered: ‎01-12-2018

Hello everyone,

Finally, answering to myself :

I was able to have I2C frames by using this vhdl code instead of an IOBUF.

i2c_sda <= s_sda_out when s_sda_dir = '0' else 'Z';
s_sda_in <= i2c_sda;
i2c_scl <= s_scl_out when s_scl_dir = '0' else 'Z';
s_scl_in <= i2c_scl;

Best regards,

View solution in original post

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