11-12-2019 02:24 AM
I am using the AXI UART16550 (2.0) IP in my Zynq Ultrascale+ design. During some specific operations where the APU is busy I am missing some data coming from the UART port. I have seen that the internal FIFO can only store 16 characters and that is not enough for my application. Given that the FIFO depth is not configurable, I would like to know if there is a way to solve this issue (e.g. connecting some AXI DMA/FIFO blocks to the UART16550). In other words, I just need a larger FIFO for the incoming data.
Thanks in advance!
11-13-2019 01:18 AM
11-12-2019 02:54 AM - edited 11-12-2019 02:55 AM
The FIFO depth isn't configurable because it's intended to match the 16550 UART (which had a 16-character buffer). I don't think you can use an AXI FIFO with it because that's designed for an AXI stream.
I can see two reasonably easy options:
- Create your own UART. A UART is not particularly complex to implement, and then you can have whatever behaviour you want - 2K buffers (each using an 18K block RAM), DMA transfers, etc.
- Create your own UART controller. HLS could do this fairly easily (essentially just a state machine that continually polls both the UART and a FIFO to see if it needs to copy data from one to the other), or a Microblaze could - or you could use one of the RPUs.\
Edit: or can you use one of the PS UARTs via EMIO? I seem to recall that they can do DMA.
11-12-2019 05:40 AM
Thanks for your prompt reply. Nevertheless my design is pretty much finished and I would like to avoid adding some new controllers or programming a UART from a scratch. Is there any way to edit that IP core? I have found the following document from Xilinx:
As my UART is instanciated in a Block Design, I guess the paragaph under "IP instance in an IP Integrator (IPI) Block Design (BD)" might be what I am looking for... Does it make sense or would it not work with the IP core I am talking about?
11-13-2019 01:18 AM