03-09-2020 06:51 AM
I created a custom HLS IP that uses simplified AXI-Stream interfaces (ready,valid,data signals only). The data is always moves on inStream and outStream interfaces, but occasionally I write or read or both to the fifo (4096 deep). I expect the fifo to be always ready as long as it is not full, regardless if the drain of the fifo (ADD block) is ready or not. However, when I try to write to the fifo, it becomes not tready. Do I need to insert any converters on the fifo ingress data pass to make it compatible with the "simplified" axi-stream interface?
03-09-2020 08:32 AM
yeah, that's understood. Just wanted to know without spending time on inspecting these interfaces. The fifo is Xilinx's IP, so I assume it is compliant. I assume that the default axi-stream interfaces generated by Vivado HLS (without my intervention) should also be compliant. But, things don't work, so maybe there's known "work around" as this is probably the common usage.
03-15-2020 03:21 AM
Given the amount of broken Xilinx AXI IP cores I've found this past year (IP packager cores, AXI slaves, AXI stream, AXI ethernet lite, AXI performance monitor, etc., etc.), I'm not sure I would assume anything is compliant. Be prepared to debug any interface you think is broken, and you should be okay.