I have noticed an issue with the AXI-Streaming FIFO in the Ultrascale+ architecture for ASYNC FIFO. When operating in Packet mode, the FIFO (with 3 or 4 CDC stages) does not strictly obey the Packet mode and sometimes introduces gaps in the tvalid signal at the read side, hence it results in an under-run at the downstream CMAC. This is a 256 deep fifo and and the packets are always 2 clk cycles long. The FIFO never gets full (at most 10 packet full based on write side rate). Is this a known issue with the ASYNC AXI-Streaming FIFO IP? There is no data loss involved and various slower clock frequencies have been tried at write side (225, 250, 275 MHz) while the read side must operate at 322 MHz. Also notice that the SYNC version of the AXI-Streaming FIFO does not exhibit this issue. Design meets timing. Simulation does now show the issue. I'm using Vivado 2020.1.