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Observer wyldecat
Observer
178 Views
Registered: ‎09-10-2019

AXI4-Stream Clock Converter doesn't create any transactions

Hi,

I used a AXI4-Stream clock converter in my block design as below.

The clock converter is connected to my RTL module and a axis dwidth converter.

But I can't see any transactions between clock converter and dwidth converter, even though there were valid transactions between mm2stream and the clock converter. 

diagram.PNG

The system ila are triggered with (mm2stream_0_m_axis_TVALID == 1) as below,

but another system ila with trigger (axis_clock_converter_0_TVALID == 1) is not triggered.

 

KakaoTalk_20191011_133422834.png

KakaoTalk_20191011_134049335.png

 

Please let me know if you have any ideas.

Any help would be greatly appreciated.

 

Thanks.

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2 Replies
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Xilinx Employee
Xilinx Employee
115 Views
Registered: ‎02-10-2015

Re: AXI4-Stream Clock Converter doesn't create any transactions

From the snippets you have posted, it looks like the connection you want to monitor is connected to system_ila_4, while you are sampling system_ila_6.  It appears that system_ila_6 is connected to the output of the axis_data_fifo.  

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Observer wyldecat
Observer
100 Views
Registered: ‎09-10-2019

Re: AXI4-Stream Clock Converter doesn't create any transactions

@ccase 

Thanks for your reply.

 

Actually, the system_ila_4 appears the hw_ila_6 in the debug window.

Also "axis_data_fifo_*" are the old name of probes. They didn't change their names even though I deleted FIFO.

 

I changed my design to use AXI interconnect's clock conversion instead of clock converter IP.

But It doesn't work either.

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