AXI4-Stream FIFO transmit not setting TKEEP on last beat
So, I have a Zynq doing DMA through into an AXI4-Stream FIFO (Cut-through, 32bit data bus). It’s doing four-beat bursts, then a few one-beat bursts. I set the stream FIFO TLR (Transmit Length Register) from the PS in the DMA-complete interrupt handler, which causes the FIFO to flush the final beat out the AXI-Stream side. All good so far.
However, one minor niggling problem. The AXI4-Stream FIFO doesn’t correctly set the TKEEP bits to null out the padding bytes of the final beat. I definitely set the precise length of the packet in the TLR, though the MM side doesn’t set WSTRB at all. Since the FIFO is waiting for the TLR to TLAST the final beat, I thought it was also waiting to TKEEP it, but TKEEP is always 0xf.
It’s a pretty minor problem all told, since ultimately the goal is to parse IP packets in PL, which have their length in the header, so having a handful of padding bytes at end of the Ethernet frame isn’t the end of the world. It’s annoying though.
Anyone ever seen this issue in the AXI4-Stream FIFO?