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mjuneja
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Registered: ‎04-26-2015

AXI4 Stream interconnect - broadcast

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Hello 

I have a query regarding AXI4 stream interconnect. Actually in my design, I have 1 AXI stream source/master which I want to broadcast to 2 AXI stream slaves. Now in order to connect, these 2 slaves to master I am using AXI4 stream interconnect in between them.

But at the output of AXI interconnect, I am getting same data at the input of both these slaves, but tvalid is not present at the input of second slave.

Is there any problem in using AXI interconnect ?

If I remove AXI interconnect, and connect all the signals of AXI master to both the slaves then the problem comes how to handle ready signals of these 2 slaves..

Please suggest.

Thanks & regards

Madhur

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mjuneja
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Sorry for the confusion @dpaul24 , actually I was looking for some Xilinx IP to provide the solution for duplicating multiple stream outputs.

So I explored AXI stream interconnect as well, but that didn't work. Finally I found AXI Stream Broadcaster IP which worked for me and the issue got resolved.

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dpaul24
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@mjuneja ,

Actually in my design, I have 1 AXI stream source/master which I want to broadcast to 2 AXI stream slaves. Now in order to connect, these 2 slaves to master I am using AXI4 stream interconnect in between them

From what I have understood a configured master can communicate with only 1 slave at a time for this IP core. You cannot do it here.

If I remove AXI interconnect, and connect all the signals of AXI master to both the slaves then the problem comes how to handle ready signals of these 2 slaves..

Exactly, that is why the AXISS is a master-slave based protocol. Just think,.............if 1 slave is busy and cannot assert the READY signal and the other slave has already made READY '1', then how will you handle this situation?

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mjuneja
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So what to do if I want to broadcast axi data stream from 1 master to more than 1 slave. And I want all the data packets from the master to reach all the slaves, so that parallel processing can happen.

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dpaul24
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@mjuneja ,

You cannot do the way you want using AXIS because I have already explained the reason. The protocol rules would be violated. Because TVALID and TREADY handshake can only happen between 1 slave and 1 master at a time.

So what to do if I want to broadcast axi data stream from 1 master to more than 1 slave. And I want all the data packets from the master to reach all the slaves, so that parallel processing can happen.

Possibly you need a design change. I don't know your design requirements, but seems you need some custom protocol for what you want to do.

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richardhead
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This will need to be a custom component.

AXIS is meant to be a point to point system. Doing "broadcast" becomes complicated because of backpressure. What happens if Slave1 is ready but Slave2 is not? You cannot simply OR together the readys to the master because SLave1 will have seen a transaction already. The valids also need to be crosswired with the opposite ready, and this gets dubious. What happens if the system is such that the ready is only high when the valid is high? then technically you cannot do this at all. This gets much more complicated the more slaves you have.

Basically this is not something that is usually done. While it can be done by "cheating" (see above) if you know your own architecture, it cannot really be done in an generic AXI compliant system.

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dgisselq
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@richardhead ,

> This will need to be a custom component.

Yes, definitely, but beyond that I'm not sure I see what the problem is.  The logic required is *really* simple.

@mjuneja ,

Check out this example of what you are looking for: one stream input, duplicated to multiple stream outputs.

It's not that hard,

Dan

richardhead
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@dgisselq 

For some reason I hadnt thought of one fifo per channel, but makes sense. As long as you're presenting a valid axi interface to the outside world, then no problem.

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mjuneja
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I don't know your design requirements, but seems you need some custom protocol for what you want to do.

@dpaul24 

Basically I want to do floating point multiplication and floating point addition using Xilinx floating point IP(7.1) where both the inputs are AXI stream based. So I was trying to connect both the inputs using AXI stream interconnect to Floating point adder and Floating point multiplier so that simultaneous processing can happen.

@dgisselq Using a FIFO seems to be a good idea, but can I use FIFO from AXI interconnect itself. I went through PG035 also, but not able to understand how packet routing to different master AXI is being handled.

 

Thanks & regards

Madhur

 

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dgisselq
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@mjuneja ,

I'm probably the wrong person to ask--I tend to avoid Xilinx's interconnect.  If I had to give an answer, I'd go with what's already been said: you will need a custom component.  The interconnect by itself is not sufficient. 

Dan

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dpaul24
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@mjuneja 

Basically I want to do floating point multiplication and floating point addition using Xilinx floating point IP(7.1) where both the inputs are AXI stream based. So I was trying to connect both the inputs using AXI stream interconnect to Floating point adder and Floating point multiplier so that simultaneous processing can happen

If you want to use another IP core which is AXIS compliant, then you have to provide data to it from another AXIS compliant source.

 

I went through PG035 also, but not able to understand how packet routing to different master AXI is being handled.

You are telling different things at different times, please make up your mind. From a previous post of yours in this thread...

So what to do if I want to broadcast axi data stream from 1 master to more than 1 slave. And I want all the data packets from the master to reach all the slaves, so that parallel processing can happen.

If you want to send data in parallel to multiple slaves from one master, you cannot use the AXIS protocol, this has been explained to you. Now you say that you are not able to understand how the AXIS Interconnect IP core works! What is it you really want to do?

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mjuneja
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Sorry for the confusion @dpaul24 , actually I was looking for some Xilinx IP to provide the solution for duplicating multiple stream outputs.

So I explored AXI stream interconnect as well, but that didn't work. Finally I found AXI Stream Broadcaster IP which worked for me and the issue got resolved.

View solution in original post

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