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Observer
Observer
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Registered: ‎02-05-2020

AXI4-Streaming XADC FIFO missing signal

I'm trying to use the DRP interface with AXI4-Stream enabled.

I'm getting the following error (failure) when I try to write a bitstream:

[DRC REQP-34] connects_RST_ACTIVE: XADC_wiz/XADC_inst/inst/AXI_XADC_CORE_I/axi4_stream_inst/FIFO18E1_inst_data: RST pin should always have ACTIVE signal for FIFO operation.

It appears that m_axis_reset is not functioning properly. 

I'm not sure how to resolve this.

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Contributor
Contributor
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Registered: ‎02-18-2019

How did you connect the reset signal to core?

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Observer
Observer
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Registered: ‎02-05-2020

@adem369  Hi adem, sorry for the delayed response.

So I have the reset signal just connected to itself because I wasn't really sure if I needed or how it would be implemented.

I noticed in the ARM documentation that reset is asynchronously asserted and must be synchronously deasserted with the rising edge of aclk - so how do I do this? Do I just connect "reset" to "aclk" in my design? That would seem to just cause reset to mimic the clock which it should not. How to would I make "reset" asynchronous in assertion and synchronous in deassertion? Is this logic already programmed in the IP so that simply connecting reset to aclk will not cause reset to just mimic aclk?

Sorry for the novice level questions. I'm trying to learn AXI.

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