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Registered: ‎03-30-2012

Artix-7 Aurora 8b10b appendix D: generating transceiver wrapper

I'm trying to replace the transceiver portion of the Aurora 8b10b core in the design I have because it doesn't match the requirements for my project, since it only generates a GT wrapper which uses PLL0, and PLL0 is already in use by a separate Aurora core in the same transceiver (one at 1.6 Gb/s rx/tx, one at 6.4 Gb/s rx/tx). I'm using Vivado 2019.2.

To do so, I've followed Appendix D of PG064 to update the transceiver wrapper file. I generated a Transceiver Wizard according to steps 1-7, with the proper protocol (Aurora 8b10b, 2 byte, single lane), line rate (1.6 Gb/s), and reference clock (PLL1, REFCLK0). According to Appendix D, step 8, in PG064, I need to:

"Replace the _gt.v[hd] and _ multi_gt.v[hd] files in the gt directory available in the Aurora 8B/10B core with the generated _gt.v[hd] and _ multi_gt.v[hd] files generated from the 7 series FPGAs transceivers wizard."

However, this step is impossible and will not work: the "_multi_gt.v" and "_gt.v" files have different module signatures between the Aurora 8b10b core and the transceiver wizard. I've attached both the _multi_gt and _gt files, the first from the Aurora 8b10b core (aux_aurora_standalone_multi_gt.v and _gt.v) and the second from the transceiver wizard (aux_aurora_gt_multi_gt.v and _gt.v).

You can see that the structure of the two files is very different: the Aurora 8b10b module (aux_aurora_standalone_multi_gt.v) takes several ports the Transceiver Wizard module does not:

  • rxcdrlock_out
  • rxpmaresetdone_out
  • txelecidle_in
  • txinhibit_in

Looking at the aux_aurora_standalone_gt.v and aux_aurora_gt_gt.v files, there are extreme differences between those, with very different GTPE2_CHANNEL attributes (the RX clock correction attributes, RX channel bonding attributes, the TX Phase Interpolator attributes), and the _gtrxreset_seq module is very different as well.

Has anyone actually used the procedure in Appendix D to replace the Transceiver Wrapper successfully? As far as I can see it doesn't work at all. I'm also including the XML files generated for the two cores.

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