Asymmetric, Dual Port Block RAM output simulation issue

[fabrizio.marchese]

Hello everyone,

I'm writing because I have a problem simulating Brams generated via Block Memory Generator 8.3 IP, and I dind't find anything on the forum.

When I simulate a design inlcuding a memory with this kind of configuration:

Mode: standalone
Mem type. both "True dual port RAM" and "Simple dual port Ram",
common clock NOT selected,
Generate address interface with 32 bits,
Port A: 256 bit, Write/Read depth: 1280 words
Port B: 64 bit


The output of the second port always generates "X"s.

This happens also whith the block memory generator example deign.

All the designs were targeted for Kintex ultrascale XCKU040 and Virtex 7 (XC7VX550).

I'm running Vivado 2016.3.

The tool used to simulate is vivado simulator.

By looking at the waveforms of simulation, it seems to me that the cause could be the internal portb address of the bmg ip, which has some bits always set to 'Z' (see image).



Has anyone else met this behaviour? Am I missing something?

Thanks for the help,
best regards,

Fabrizio

[morgan198510]

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@fabrizio.marchese wrote:

Hello everyone,
...

Has anyone else met this behaviour? Am I missing something?

Thanks for the help,
best regards,

Fabrizio

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@fabrizio.marchese My guess is you're missing the fact that some of the bits on the port b address bus are high impedance 'Z'.

[fabrizio.marchese]

Thanks for replying.

I'm pretty sure too the problem lies in some bits of thet address being set to 'Z', bat that address highlighted in the waveform is an internal address of bmg encrypted hdl, so it is neither editable nor accessible.

Before entering the bgm hdl block, both adresses are perfectly ok.

And I've checked also that there are not some strange signal values at the beginning of the simulation.

But, as already entioned, also IP generated example design fails.

I've found the problem arises only when the simulator langage is set to "mixed", when setting language to "VHDL" or "Verilog" (but the simulation runs much slower than same project in Vivado2015.2)

[vemulad]

Hi @fabrizio.marchese

Can you share example design project archive?

[fabrizio.marchese]

Yes, of course.

[vemulad]

Hi @fabrizio.marchese

This looks to be an issue with behavioral model, post synthesis simulation is working fine. Please check the same at your end.

[fabrizio.marchese]

Thanks Deepika,

Yes, it's working fine.

Is there something to do to fix behavioral simulation? Thetestbench I'm using these BRAMs in is pretty big, and post synthesis simulation is pretty slow.

[vemulad · Accepted solution]

Hi @fabrizio.marchese

This issue is not seen in behavioral simulation in vivado 2017.1. Vivado 2017.1 is scheduled for release in next quarter, is it possible for you to wait for the release and upgrade your design?

[fabrizio.marchese]

Yes,

no problem.

Thanks again.