09-01-2020 01:30 PM
Hello, I am using the Zynq Ultrascale+ MPSoC on a custom board. I have manged to get the Aurora IP working on the ZCU106 board and now I'm reading to get it running on my custom board.
I am running the xaxi_dma_example_simple_poll.c program. I have set the loopback to  which is a near-end PCS loopback. I am getting
Channel UP high and Lane UP high, no Hardware or Software Errors.
Also, qt_pll_lock is high.
The problem I am seeing is that the code never exits the CheckData():
I assume that the DMA to the Aurora and from the Aurora is good but for some reason the code hangs here:
I have attached the TCL of my Vivado so you regenerate the block diagram if needed. I've also include my Vitis projects. I am using Vivado/Vitis 2019.2
If anyone can help me that would great.
09-01-2020 02:11 PM
09-01-2020 05:24 PM
Hello, thank you very much for responding to my message. No I did not. I'm not familiar with what you are referring to. Is that somewhere in the C code or are you referring to an IP setting on the Vivado IP blocks?
On the ZCU106 I only ran the example c program and it worked so I must be missing something here.
Thank you very much,
09-01-2020 05:57 PM
09-02-2020 07:19 AM
When the Loopback is in Normal Mode I'm not getting gt_pll_lock high. When I put the Loopback in Near-End PCS Loopback or Near-End PMS Loopback then I Channel Up, Lane UP, and gt_pll_lock high. I need to trouble the Normal mode more.
When the loopback in is Near-end PCS or PMA then in the code it never returns from CheckData() function that I mentioned above.
Thank you for helping me.
09-02-2020 07:31 AM
09-02-2020 07:09 PM
I'm doing some more trouble shooting and I believe my trouble is that on power-up the reset_pb is not high while the pma_int is high while in normal mode. Will investigate tomorrow.
09-09-2020 10:30 AM
I fixed the Power ON Reset and now match Figure 3-2 page 68 of Aurora 64B/66B PG074 documentation.
In loopback Normal Mode I don't get a solid gt_pll_lock. I is going low periodically.
What could this mean?