Aurora 64B/66B LoopBack

[joe306]

Hello, I am using the Zynq Ultrascale+ MPSoC on a custom board. I have manged to get the Aurora IP working on the ZCU106 board and now I'm reading to get it running on my custom board.

I am running the xaxi_dma_example_simple_poll.c program. I have set the loopback to [001] which is a near-end PCS loopback. I am getting
Channel UP high and Lane UP high, no Hardware or Software Errors.
Also, qt_pll_lock is high.
The problem I am seeing is that the code never exits the CheckData():

I assume that the DMA to the Aurora and from the Aurora is good but for some reason the code hangs here:

I have attached the TCL of my Vivado so you regenerate the block diagram if needed. I've also include my Vitis projects. I am using Vivado/Vitis 2019.2

If anyone can help me that would great.

Respectfully,

Joe

[joe306]

I've uploaded my Vitis project.

[joe306]

I've noticed when I put the Loopback in Near-end PCS or Near-end PMA then I get a Lane Up and Channel UP and the qt_pll_lock is high. However, when I try the loopback in Far-end PMA/PCS then I don't get Lane Up or Channel UP and qt_pll_lock is low.
Hope this helps.
Joe

[joe306]

Okay, I've ran the code a few times and it is hanging in the following:

Any ideas? I'm looking over UG576 page 86/87 for ideas.

Thank you

Joe

[watari]

Hi @joe306 

I'm not sure. But I ask you.

Did you make sure parameter and status on XDMA ?

It might be insufficient on XDMA...

Best regards,

[joe306]

Hello, thank you very much for responding to my message. No I did not. I'm not familiar with what you are referring to. Is that somewhere in the C code or are you referring to an IP setting on the Vivado IP blocks?

On the ZCU106 I only ran the example c program and it worked so I must be missing something here.

Thank you very much,

Joe

[joe306]

Correct if I'm wrong here. I may have some confusion with page 86 of UG576 Figure 2-27. Is this figure showing two PCB boards connected together? I believe it is and if so, then I am not doing that. I'm only using one board and the Aurora IP is connected to a Fast Fiber transceiver and I only loop the fiber cable back from the TX to RX port. That is the trouble I am having, doing a simple loopback in Normal mode. I'll send some more information tomorrow that will show where the code hangs in Normal mode.
Thank you very much.
Joe

[joe306]

When the Loopback is in Normal Mode I'm not getting gt_pll_lock high. When I put the Loopback in Near-End PCS Loopback or Near-End PMS Loopback then I Channel Up, Lane UP, and gt_pll_lock high. I need to trouble the Normal mode more.

When the loopback in is Near-end PCS or PMA then in the code it never returns from CheckData() function that I mentioned above.

Any ideas?

Thank you for helping me.

Joe

[joe306]

I'm looking on page 86 of UG576 and I am not doing:
The RX elastic buffer must be enabled and RX_XCLK_SEL must be set to RXDES for
near-end PCS loopback to function properly. While in near-end PCS loopback, the RX
XCLK domain is clocked by the TX PMA parallel clock (TX XCLK). If the RXOUTCLK is used
to clock interconnect logic and RXOUTCLKSEL is set to RXOUTCLKPMA during normal
operation, one of these two items must be changed when placing the GTH transceiver
into near-end PCS loopback:
° Set RXOUTCLKSEL to select RXOUTCLKPCS, or
° Set RXCDRHOLD = 1'b1

I need to figure out how to do this. I don't see these ports on my Aurora IP Block.

Joe

[joe306]

[joe306]

I'm doing some more trouble shooting and I believe my trouble is that on power-up the reset_pb is not high while the pma_int is high while in normal mode. Will investigate tomorrow.

Thank you,

Joe

[joe306]

I fixed the Power ON Reset and now match Figure 3-2 page 68 of Aurora 64B/66B PG074 documentation.

In loopback Normal Mode I don't get a solid gt_pll_lock. I is going low periodically.

What could this mean?

Thank you,

Joe