05-14-2021 08:46 AM
This is not a question. For anyone who has tried simulating the Aurora 64b/66b v12 core and have it run for 12+ hours and the channel never going up, you can thank Xilinx for not fixing this issue for the LONGEST time. If you have the simulator language on VHDL, change it to Verilog and regenerate the core. Then the testbench will finish in about 2 minutes.
YOURE WELCOME. I am sending Xilinx the electric bill for running my computer over night. Thanks