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Registered: ‎11-12-2019

Aurora 64b/66b

Vivado validation results in following warnings and errors! I wonder how  to resolve them? Please let me know as it is urgent I resolve these in  order to simulate the block. I attach my block diagram in zip format for reference. Thanks

 

General Messages[BD 41-1363] The clock pins '/axi_interconnect_0/M01_ACLK' (interface '/axi_interconnect_0/M01_AXI') and '/AXI_C2C_S/axi_chip2chip_0_aurora64/init_clk' (interface '/AXI_C2C_S/axi_chip2chip_0_aurora64/AXILITE_DRP_IF_0') must be connected to the same source
[xilinx.com:ip:aurora_64b66b:11.2-5910] /AXI_C2C_S/axi_chip2chip_0_aurora64 ERROR : INIT_CLK setting is in manual mode, update init_clk GUI i/p of /AXI_C2C_S/axi_chip2chip_0_aurora64 (Aurora IP) with init_clk frequency 25000000 Hz being connected to port
[BD 41-237] Bus Interface property FREQ_HZ does not match between /AXI_C2C_S/axi_chip2chip_0_aurora64/USER_DATA_S_AXIS_TX(161132813) and /AXI_C2C_S/axi_chip2chip_0/AXIS_TX(50002248)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /AXI_C2C_S/axi_chip2chip_0_aurora64/refclk1_in(156250000) and /I_AXI_C2C_REFCLK(100000000)
[BD 41-1031] Hdl Generation failed for the IP Integrator design /rfs/proj/cop2sim/Fardad/trunk/project_2/project_2.srcs/sources_1/bd/aurora_blk/aurora_blk.bd
aurora_blkGeneral Messages[BD 41-758] The following clock pins are not connected to a valid clock source:
/AXI_C2C_S/axi_chip2chip_0/axi_c2c_phy_clk
/AXI_C2C_S/axi_chip2chip_0_aurora64/user_clk
/AXI_C2C_S/axi_chip2chip_0_aurora64/sync_clk
/AXI_C2C_S/axi_chip2chip_0_aurora64/gt_qpllclk_quad1_in
/AXI_C2C_S/axi_chip2chip_0_aurora64/gt_qpllrefclk_quad1_in
/clk_wiz_0/clk_in1

[BD 41-1031] Hdl Generation failed for the IP Integrator design /rfs/proj/cop2sim/Fardad/trunk/project_2/project_2.srcs/sources_1/bd/aurora_blk/aurora_blk.bd
[xilinx.com:ip:aurora_64b66b:11.2-5910] /AXI_C2C_S/axi_chip2chip_0_aurora64 ERROR : INIT_CLK setting is in manual mode, update init_clk GUI i/p of /AXI_C2C_S/axi_chip2chip_0_aurora64 (Aurora IP) with init_clk frequency 25000000 Hz being connected to port
[BD 41-237] Bus Interface property FREQ_HZ does not match between /AXI_C2C_S/axi_chip2chip_0_aurora64/USER_DATA_S_AXIS_TX(161132813) and /AXI_C2C_S/axi_chip2chip_0/AXIS_TX(50002248)
[BD 41-238] Port/Pin property FREQ_HZ does not match between /AXI_C2C_S/axi_chip2chip_0_aurora64/refclk1_in(156250000) and /I_AXI_C2C_REFCLK(100000000)
[BD 41-1363] The clock pins '/axi_interconnect_0/M01_ACLK' (interface '/axi_interconnect_0/M01_AXI') and '/AXI_C2C_S/axi_chip2chip_0_aurora64/init_clk' (interface '/AXI_C2C_S/axi_chip2chip_0_aurora64/AXILITE_DRP_IF_0') must be connected to the same source
[IP_Flow 19-3478] Validation failed for parameter 'My M00_A00_ADDR_WIDTH(M00_A00_ADDR_WIDTH)' with value '16' for BD Cell 'axi_interconnect_0/xbar'. PARAM_VALUE.M01_A00_BASE_ADDR overlaps with address segment PARAM_VALUE.M00_A00_BASE_ADDR
[BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
::xilinx.com_ip_axi_crossbar_2.1::post_propagate Line 54
[BD 41-1680] There are two paths between /AXI_C2C_S/axi_chip2chip_0/m_axi and /AXI_C2C_S/axi_chip2chip_0_aurora64/AXILITE_DRP_IF_0
[BD 41-1681] Duplicate paths (A , B) listed below
/AXI_C2C_S/axi_chip2chip_0/m_axi
/AXI_C2C_S/m_axi
/AXI_C2C_S/m_axi
/axi_interconnect_0/S01_AXI
/axi_interconnect_0/s01_couplers/S_AXI
/axi_interconnect_0/s01_couplers/auto_cc/S_AXI
/axi_interconnect_0/s01_couplers/auto_cc/M_AXI
/axi_interconnect_0/s01_couplers/M_AXI
/axi_interconnect_0/s01_couplers/M_AXI
/axi_interconnect_0/xbar/S01_AXI
* A /axi_interconnect_0/xbar/M00_AXI
* B /axi_interconnect_0/xbar/M01_AXI
* A /axi_interconnect_0/m00_couplers/S_AXI
* B /axi_interconnect_0/m01_couplers/S_AXI
* A /axi_interconnect_0/m00_couplers/auto_cc/S_AXI
* B /axi_interconnect_0/m01_couplers/auto_cc/S_AXI
* A /axi_interconnect_0/m00_couplers/auto_cc/M_AXI
* B /axi_interconnect_0/m01_couplers/auto_cc/M_AXI
* A /axi_interconnect_0/m00_couplers/M_AXI
* B /axi_interconnect_0/m01_couplers/auto_pc/S_AXI
* A /axi_interconnect_0/m00_couplers/M_AXI
* B /axi_interconnect_0/m01_couplers/auto_pc/M_AXI
* A /axi_interconnect_0/M00_AXI
* B /axi_interconnect_0/m01_couplers/M_AXI
* A /axi_interconnect_0/M00_AXI
* B /axi_interconnect_0/m01_couplers/M_AXI
* A /axi_interconnect_0/S00_AXI
* B /axi_interconnect_0/M01_AXI
* A /axi_interconnect_0/s00_couplers/S_AXI
* B /axi_interconnect_0/M01_AXI
* A /axi_interconnect_0/s00_couplers/auto_cc/S_AXI
* B /AXI_C2C_S/AXILITE_DRP_IF_0
* A /axi_interconnect_0/s00_couplers/auto_cc/M_AXI
* A /axi_interconnect_0/s00_couplers/M_AXI
* A /axi_interconnect_0/s00_couplers/M_AXI
* A /axi_interconnect_0/xbar/S00_AXI
* A /axi_interconnect_0/xbar/M01_AXI
* A /axi_interconnect_0/m01_couplers/S_AXI
* A /axi_interconnect_0/m01_couplers/auto_cc/S_AXI
* A /axi_interconnect_0/m01_couplers/auto_cc/M_AXI
* A /axi_interconnect_0/m01_couplers/auto_pc/S_AXI
* A /axi_interconnect_0/m01_couplers/auto_pc/M_AXI
* A /axi_interconnect_0/m01_couplers/M_AXI
* A /axi_interconnect_0/m01_couplers/M_AXI
* A /axi_interconnect_0/M01_AXI
* A /axi_interconnect_0/M01_AXI
* A /AXI_C2C_S/AXILITE_DRP_IF_0
/AXI_C2C_S/axi_chip2chip_0_aurora64/AXILITE_DRP_IF_0

 

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