05-04-2021 06:35 AM
I am designing a link between two FPGAs with aurora 8b/10b. I am having lane_up and channel_up high in one side (FPGA B Slave Kintex) while they are always low at the other side (FPGA A Master Zynq Ultrascale).
Can anyone know how to solve this issue?
05-04-2021 07:55 AM
Just guessing it could be the reset procedure. You would need reset the TX channels before you reset the RX channels. If you do reset all, which is common, there is a decent chance you will be resetting an RX channel without a stable TX input which can lead to problems because the Clock data recovery circuit needs a stable input to reach the proper clock speed.
05-04-2021 03:00 PM
Hi Roym, Thanks for your reply.
The reset to aurora is provided by chip2chip component, can you please specify how I can reset the TX before the RX. I attached the hw_ila which shows the result of the reset process.