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Anonymous
Not applicable
14,747 Views

Aurora 8b10b data lost

I have a design including TX and RX simplex core each.

 

My cores are single lane 2Gbps data rate. 

lane width = 2 bytes

refclk = 125Mhz

framing interface

no flow control

back channel = sidebands

scrambler/descrambler = enabled

CRC enabled

 

I am using example design for both rx and tx cores. the only difference is the TX core is transmitting one hot patterns i.e

 

0000000000000001

0000000000000010

0000000000000100

       .

       .

1000000000000000

 

I want to have a loopback of these cores in single FPGA (AC701 board) for test purpose.

 

In simulation, everything is fine, all error signals are low and all channel up and lane up signals are high through out.

The problem is :

Rx core is missing data beats. like what i receive is 

 

0000000000000001

0000000000010000

0000000000100000

0001000000000000

 

 

In the end, I have connected the cores in top module like

 

aurora_8b10b_tx_exdes #
(
.USE_CHIPSCOPE (0),
.USE_CORE_TRAFFIC (1)
)
AURORA_TX_TOP
(
// User IO
.RESET (reset),
.TX_HARD_ERR                    (TX_HARD_ERR),    // for debug.when asserted--> aurora core is reset
.TX_LANE_UP                         (TX_LANE_UP),            // for debug
.TX_CHANNEL_UP                (TX_CHANNEL_UP), // for debug

.GTPQ0_P                               (GTPQ0_P),
.GTPQ0_N                               (GTPQ0_N),


//Simplex Sideband Signals
.TX_ALIGNED                    (TX_ALIGNED),
.TX_VERIFY                        (TX_VERIFY),
.TX_RESET                        (TX_RESET),

// GT I/O

.TXP                                     (TXP),
.TXN                                     (TXN),

.INIT_CLK_P                      (1'b0), // init_clk given through DCM internally
.INIT_CLK_N                     (1'b0),
.DRP_CLK_IN                   (1'b0),
.GT_RESET_IN                (reset)
);

 

aurora_8b10b_rx_exdes #
(
.USE_CHIPSCOPE (0),
.USE_CORE_TRAFFIC (1)
)
AURORA_RX_TOP
(
// User IO
.RESET                           (reset),
.RX_HARD_ERR           (RX_HARD_ERR),
.SOFT_ERR                   (SOFT_ERR),
.FRAME_ERR               (FRAME_ERR),
.RX_LANE_UP             (RX_LANE_UP),
.RX_CHANNEL_UP    (RX_CHANNEL_UP),

// CRC Status
.CRC_PASS_FAIL_N    (), // not used
.CRC_VALID                  (), // not used


.GTPQ0_P                       (GTPQ0_P),
.GTPQ0_N                       (GTPQ0_N),

 

//Simplex Sideband Signals
.RX_ALIGNED              (TX_ALIGNED),
.RX_VERIFY                 (TX_VERIFY),
.RX_RESET                  (TX_RESET),


// Frame check interface
.ERR_COUNT                  (),

// GT I/O
// .RXP                               (RXP),
// .RXN                              (RXN),
.RXP                                  (TXP),
.RXN                                  (TXN),

.INIT_CLK_P                    (1'b0), // init_clk given through DCM internally
.INIT_CLK_N                     (1'b0),
.DRP_CLK_IN                 (1'b0), // not used
.GT_RESET_IN              (reset)
);

Tags (2)
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17 Replies
venkata
Moderator
Moderator
14,734 Views
Registered: ‎02-16-2010

Any reason for sending one hot pattern....can you test the link with a different pattern to confirm if the issue is pattern dependent.

enabling CRC will help to know the data miss in the form of CRC error.... but as per the instantiation above, it looks like you are not using the CRC outputs...
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Anonymous
Not applicable
14,730 Views

sending one hot pattern just to visually confirm received data. 

 

Thought to disable scrambler descrambler and now...no channel up and lane up :(

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venkata
Moderator
Moderator
14,703 Views
Registered: ‎02-16-2010

how are you doing this? Are you generating a different core without scrambler/descrambler?
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Anonymous
Not applicable
14,694 Views

I have re generated same core with scrambler disabled

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Anonymous
Not applicable
14,689 Views

Is this problem solving service of a top notch FPGA company? people hired for solving problems should take them seriously and persue until its solved.... 24 hours i have posted the problem and no one cares to solve it.

PATHETIC

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mcgett
Xilinx Employee
Xilinx Employee
14,662 Views
Registered: ‎01-03-2008

> Is this problem solving service of a top notch FPGA company?

 

The Xilinx User Forums are a community based resource.  While there are many Xilinx employees that participate in the forums this is not an official support channel.   Please discuss with your FAE or Sales representative about options for official support.

 

Note: If I had an suggestions for your issue above, I would make them but I do not based on your problem description and my knowledge base.   In general the more information that you provide about the system, conditions and debug that you have done the better chance that you have for some in the community to recognize where the problem may be.  In your case above you have not described how you achieved the loopback on the AC701 board,  you have not provided a full interface for the Aurora TX and RX simplex blocks, nor described how you have connected ChipScope ILA to the Aurora cores.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Anonymous
Not applicable
14,654 Views

-->" In your case above you have not described how you achieved the loopback on the AC701 board,  you have not provided a full interface for the Aurora TX and RX simplex blocks, nor described how you have connected ChipScope ILA to the Aurora cores."

 

The problems you have pointed out in my problem definition clearly shows how thoroughly you have read my question.

 

- It is clearly mentioned it's simulation , so no question of chipscope.

- the code i pasted in the end of my question clearly shows how two cores are connected in loopback in top module. 

  TXp and TXP are connected to RXP and RXN respectively.

 

So you have elaborated more how xilinx employees read questions.

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mcgett
Xilinx Employee
Xilinx Employee
14,637 Views
Registered: ‎01-03-2008

In your original post you wrote:

 

> I want to have a loopback of these cores in single FPGA (AC701 board) for test purpose.

>

> In simulation, everything is fine, all error signals are low and all channel up and lane up signals are high through out.

 

My reading of this is that your simulation worked fine and you had problems in hardware testing.

 

Can you please attach the entire top level HDL code and if you are using a test bench that code as well for review?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Anonymous
Not applicable
14,603 Views

I am working in a company not a university. Thank you very much for your prompt response. I have solved problem myself.

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mimitter
Contributor
Contributor
11,630 Views
Registered: ‎05-02-2011

how do I salve the question, I also occur the same question in Aurora 8b/10b IP

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mcgett
Xilinx Employee
Xilinx Employee
11,624 Views
Registered: ‎01-03-2008

> I have solved problem myself.

 

I am glad that you have resolved the problem.  Can you please explain what you did to solve the problem to help others in the future?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Anonymous
Not applicable
11,616 Views

In tx_frame_gen.v file, My signals were working fine standalone but i didnt check whether the interface signals (S_AXI_TX_TDATA,S_AXI_TX_TREADY,S_AXI_TX_TLAST, S_AXI_TX_TKEEP,S_AXI_TX_TVALID) are going correctly in aurora core or not . when i added aurora core signals(in tx_exdes.v file.) in simulation window , there was timing mismatch.

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zqlxinyu
Observer
Observer
10,719 Views
Registered: ‎09-01-2013

Hi,can the aurora lost the rx_sof when the tx_sof,tx_eof and tx_src is sent correctly? thanks!

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venkata
Moderator
Moderator
10,679 Views
Registered: ‎02-16-2010

Please start a different thread.
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dourenyin
Newbie
Newbie
9,541 Views
Registered: ‎03-30-2015

Hi, a4speaker!

I want to know how do you solve the problem. I have encountered the same issue recently when I have two fpgas connected with four lanes' aurora link.

Waiting for your reply!

Thank you very much!!!!!

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venkata
Moderator
Moderator
9,523 Views
Registered: ‎02-16-2010

Have you checked the solution mentioned by him?

"In tx_frame_gen.v file, My signals were working fine standalone but i didnt check whether the interface signals (S_AXI_TX_TDATA,S_AXI_TX_TREADY,S_AXI_TX_TLAST, S_AXI_TX_TKEEP,S_AXI_TX_TVALID) are going correctly in aurora core or not . when i added aurora core signals(in tx_exdes.v file.) in simulation window , there was timing mismatch."
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molihua08
Contributor
Contributor
218 Views
Registered: ‎07-12-2018

have it solved? I have the same situation.

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