I have two Aurora 8b10b cores that form a bidirectional link between two different Xilinx KU060 FPGAs, and I have been running a BIST that sends test data from a generator in FPGA A to a comparator in FPGA B. Most of the time, the link works perfectly ... but on rare occasions, I reach the end of my test, and the last three words don't come out of the core on the receive side. If I command the generator to send some more data, the final three words of the previous frame get flushed out -- so no data is actually lost. The Aurora protocol is holding it in a buffer somewhere.
I am operating the cores in framing mode. The AXIS interface to the Aurora core is 128 bits wide, and I generate a "last" pulse every 512 words, meaning that the frames are consistently sized at 512 128-bit words each. So three words is a small fraction of a frame. Again, this is a rare problem: usually the last frame I send emerges in its entirety. But now and then, a few words at the end of the last frame fail to emerge, and the number of trapped words is always three.
I am not seeing any bit errors or other signs of poor signal integrity. What could cause either the TX or the RX core to hold on to data this way?
Vivado version: 2017.3
Core and link specs: 8b10b encoding, 4 channel-bonded lanes, bidirectional, clock compensation in use, 5 Gbps line rate
