Aurora Chip2Chip Config Error?

[mattwaltz]

Hello, I am using the AXI Chip2Chip core in tandem with the Aurora 64/66B core. I am detecting 'channel up' and 'lane up' across all lanes from the Aurora core, and no other error statuses from the Aurora core. However, the Chip2Chip core outputs a 'config_error' status, and never asserts the Chip2Chip link. I have checked that the ID and USER widths are the same in both the slave and the master.

What could be causing the Chip2Chip core to be outputting a configuration error? According to the FSM, it's only when the slave doesn't respond with some "pattern" within a set amount of time. However, the Aurora core says that the channel is up? Could it potentially be a wire length issue or something odd like that?

The Aurora Link is rated at 5Gb/sec with 3 Lanes. The hardware is more than capable of supporting this.

Any advice or description of what can cause a configuration error would be much appreciated.

[mattwaltz · Accepted solution]

I solved this by setting up an ILA on both the receive/transmit sides of the Aurora link, and the same on the other board. I noticed that the data was shifted; because I was using 3 lanes, lane 1 data was going into lane 3, and lane 3 data into lane 1. Simply swapping the lane wire connections allows everything to work. I blame whoever wrote the pinout documentation for the board I am working with.