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Contributor
Contributor
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Registered: ‎03-16-2018

Aurora MGT clock selection

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When using the aurora IP on an Ultrascale+ design is it possible to specify the MGT clock to use the clock of an adjacent quad (north/south)?  The wizard only allows selection of MGTREFCLK0/1 of the quad with the single TX/RX lanes that are configured to be used.  

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @hmleland.mms.rf 

Yes. It is possible.
Aurora GUI will generate a "set_property LOC" constraint in XDC. You can easily modify this XDC fit your usecase.

################################################################################
## XDC generated for xcku040-ffva1156-2 device
# 125.0MHz GT Reference clock constraint
create_clock -name GT_REFCLK1 -period 8.0 [get_ports GT_REFCLK_P]
# Reference clock location
set_property LOC AB6 [get_ports GT_REFCLK_P]
set_property LOC AB5 [get_ports GT_REFCLK_N]
####################### GT reference clock LOC #######################

Please let me know if you have difficulity on this.


Thanks
Leo

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Xilinx Employee
Xilinx Employee
402 Views
Registered: ‎03-30-2016

Hello @hmleland.mms.rf 

Yes. It is possible.
Aurora GUI will generate a "set_property LOC" constraint in XDC. You can easily modify this XDC fit your usecase.

################################################################################
## XDC generated for xcku040-ffva1156-2 device
# 125.0MHz GT Reference clock constraint
create_clock -name GT_REFCLK1 -period 8.0 [get_ports GT_REFCLK_P]
# Reference clock location
set_property LOC AB6 [get_ports GT_REFCLK_P]
set_property LOC AB5 [get_ports GT_REFCLK_N]
####################### GT reference clock LOC #######################

Please let me know if you have difficulity on this.


Thanks
Leo

View solution in original post

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Contributor
Contributor
398 Views
Registered: ‎03-16-2018

Leo,

 

Thanks, just wanted to make sure that the wizard was not generating other GT config that would need to be changed as well as the pin location constraint.  I am not sure why the pin selection is in the wizard then.  The tool must create a default location constraint for the clock pins?

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Xilinx Employee
Xilinx Employee
386 Views
Registered: ‎03-30-2016

Hello @hmleland.mms.rf 

We have transceiver quad selection on wizard GUI, so wizard can generate the pin assignment automatically.
User can modify this generated XDC if necessary.

Regards
Leo

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