In Aurora 64B/66B,
I am using XC7VX550T-2FFG1927I FPGA. i have attached snapshots of Aurora physical layer and link layer settings, DRP mode is disabled for 12 lanes.
Once we done simulation by selected powerdown is 0 and loopback [2:0] is 1. then after 22 us, lane up and channel up both become active HIGH. but TX_TREADY signal not become active HIGH. PFA