06-17-2021 11:58 PM
If i want to transfer data from one FPGA to another using Aurora IP, should i make one IP master in one FPGA and the other one slave in the other FPGA?
06-18-2021 11:40 AM
Hi @vhdlveri123 ,
Not necessary but again depends on the targeted application.
06-29-2021 02:46 AM
Yes you can do clock sharing but please make sure reference clock is passing GT phase noise mask.