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Visitor
Visitor
841 Views
Registered: ‎10-31-2018

Aurora64 not working with GTY transceiver?

I am trying to setup a serial connection between two boards (VC707 and ) by using the Aurora64 IPcore. I could easily setup the connection on the VC707, and tested it with another VC707 in duplex mode at a line rate of 6.25GBps. Unfortunately, I have not been able to achieve the same result on the XUPVVH board based on the VU37P FPGA.

Is there any specific thing to do in order to use the GTY transceivers? I am using one of the QSFP+ cage  adapted to a SFP+ to connect it to the VC707. The Aurora core does not seem to initialize (lane_up and channel_up are not asserting, and user_clk is not working).

I attached a capture of the Aurora IPcore PHY.

 

Thanks,

David

 

 

 

auroraGTYconfig.PNG
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5 Replies
Xilinx Employee
Xilinx Employee
811 Views
Registered: ‎08-07-2007

hi @dacabad 

 

is user_clk at the correct frequency? (line rate divided by 64)

or it is flat line?

 

Thanks,

Boris

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Visitor
Visitor
789 Views
Registered: ‎10-31-2018

I have been doing some extra testing and it seems that setting the gtrefclk at a 322.265625Hz the user_clk works properly. However, at any other rate, the core seems to not work at all. In any case, the lane_up and channel_up do not assert, and the t_ready from the TX AXI stream is also staying low.

I tested the communication over two VC707 boards setting the refclk to different frequencies (125MHz and 156MHz respectively). I thought that this should not affect the communication between both, but as far as I can tell, they seem to only be able to start communicating when the gtrefclk has the same value for both Aurora cores. Is this the expected behaviour?

Kind regards,

David

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Participant
Participant
572 Views
Registered: ‎08-15-2019

Hi guys,

 

I am having the same problem. 

My settings are:

kit: Ultrascale+ vcu118 xcvup9;

Aurora64b;

Line rate; 5 Gbps;

GT Refclk: 125  or 156.25MHz  (with either values i got same situation)

Transceivers: GTY;

Pin:  connection to the FMC connector 33 on which is plugged a FM-S14  (SFP card)

DRP mode: Native;

Shared logic: included in the code;

 

Wheter I run a loopback test or connect the fpga to another simulator to exchange frames, 

the Aurora core never gets ready in the sense that s_axi_tx_tready stays always to 0  and the user_clk_out, channel_up and lane_up stays to 0 as well.

 

The ONLY case when the system works is in the BEHAVIORAL SIMULATION.

 

Also the AURORA 64 EXAMPLE FROM XILINX NEVER WORKS.  

 

Do you guys have any ideas ?

 

Thanks
Regards

 

        

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Participant
Participant
535 Views
Registered: ‎08-15-2019

@borisqcould you please give me any  suggestions related to my question ?

 

Thanks

Regards

Mike

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Xilinx Employee
Xilinx Employee
496 Views
Registered: ‎08-07-2007

hi @dacabad 

 

 

did you test ibert? we need to rule out hardware issue first. 

 

Thanks,

Boris

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