06-17-2020 06:11 AM
I am trying to quickly setup a loopback configuration for my part (xczu15eg-ffvb1156-1-i) using the Aurora 64b66b IP in Xilinx Vivado 2019.2 for the Zynq Ultrascale+. I was wondering if Xilinx has any example designs that use the transceiver capabilities of the aurora 64b66b IP. Namely, information on how to setup the transceiver/clock/reset/etc pins properly (in the vhdl architecture and block design). If nothing exists for my current setup, are there any example designs for different part/FPGA combinations that I could build off of?
06-22-2020 02:53 AM
Hi @aakhmedov ,
Please refer to "example design" Section of PG074.
06-29-2020 07:38 AM
I setup a design using Xilinx Aurora 64B66B IP as well as my own waveform wrapper IP (migrated from Vivado 2015.4). I didn't get any errors during synthesis or implementation. But upon analyzing my implementation, I can see that the tx connections are not setup. It seems that the rx connections are created however. The log file associated with this run is attached.
06-29-2020 10:28 AM - edited 06-29-2020 11:27 AM
I am attaching an image of my implementation. You can see that that receive side pins are connected (on left) but the transmit side isn't connected at all.