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egatard
Visitor
Visitor
861 Views
Registered: ‎06-20-2018

BRAM Controller resources utilization with Read Latency feature

Hello,

Since Vivado 2018.3 there is the possibility to configure the read latency from BRAM in the BRAM controller IP, so the controller can work with BRAM with output registers.

I would like to use this feature, but then resources utilization goes from 1700 FF & 458 LUT to 1700FF and a whopping 11000 LUT.

Is this expected behavior?

Here is the IP configuration:

bram.png

 

This feature would be usefull to be able to close timing in my design, but the huge LUT count outweighs the benefits of the BRAM output registers.

 

Thanks

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pthakare
Moderator
Moderator
849 Views
Registered: ‎08-08-2017

Hi @egatard 

I will check the resource utilization for READ_LATENCY = 1 and 2  for the IP example design and update you soon.

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pthakare
Moderator
Moderator
810 Views
Registered: ‎08-08-2017

Hi @egatard 

I checked the resource utilization for READ_LATENCY = 1 and 2  for the IP example design .

1. Resource utilization for  READ_LATENCY =1

 

read_latency1.JPG

2. Resource utilization for  READ_LATENCY =2

read_latency2.JPG

I am not getting the much deviation as you reported.  Can you share your project to check at our end?

 

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egatard
Visitor
Visitor
802 Views
Registered: ‎06-20-2018

Hello,

Thank you for looking into this.

Sorry, but i won't be able to share this project.

To start on clean basis I used the reset_project command then re-synthesized the whole project using the Vivado Synthesis Default strategy.

I am using Vivado 2018.3.

I started with READ_LATENCY = 1 and i got this:

 

+----------------------------+------+-------+-----------+-------+
|          Site Type         | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| CLB LUTs*                  |  458 |     0 |    242400 |  0.19 |
|   LUT as Logic             |  457 |     0 |    242400 |  0.19 |
|   LUT as Memory            |    1 |     0 |    112800 | <0.01 |
|     LUT as Distributed RAM |    0 |     0 |           |       |
|     LUT as Shift Register  |    1 |     0 |           |       |
| CLB Registers              | 1706 |     0 |    484800 |  0.35 |
|   Register as Flip Flop    | 1706 |     0 |    484800 |  0.35 |
|   Register as Latch        |    0 |     0 |    484800 |  0.00 |
| CARRY8                     |    1 |     0 |     30300 | <0.01 |
| F7 Muxes                   |    0 |     0 |    121200 |  0.00 |
| F8 Muxes                   |    0 |     0 |     60600 |  0.00 |
| F9 Muxes                   |    0 |     0 |     30300 |  0.00 |
+----------------------------+------+-------+-----------+-------+

This result is similar to what you obtained.

 

Then i simply changed to READ_LATENCY = 2 and i got this:

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| CLB LUTs*                  | 11809 |     0 |    242400 |  4.87 |
|   LUT as Logic             |  2432 |     0 |    242400 |  1.00 |
|   LUT as Memory            |  9377 |     0 |    112800 |  8.31 |
|     LUT as Distributed RAM |  9376 |     0 |           |       |
|     LUT as Shift Register  |     1 |     0 |           |       |
| CLB Registers              |   817 |     0 |    484800 |  0.17 |
|   Register as Flip Flop    |   817 |     0 |    484800 |  0.17 |
|   Register as Latch        |     0 |     0 |    484800 |  0.00 |
| CARRY8                     |     2 |     0 |     30300 | <0.01 |
| F7 Muxes                   |  1024 |     0 |    121200 |  0.84 |
| F8 Muxes                   |   512 |     0 |     60600 |  0.84 |
| F9 Muxes                   |     0 |     0 |     30300 |  0.00 |
+----------------------------+-------+-------+-----------+-------+

I attached the synthesis reports and utilization reports for the two cases.

 

When I open the the synthesized OOC run of the BRAM controller, the resources utilization looks like this:

BRAM_ctrl_utilization.png

In the schematic, there is a lot of RAM64M8 instances with BRAM read data at their input and a lot of muxes at their outputs.

The output port the the VHDL when the BRAM are inferred is configured like this:

BRAM_port.png

The AXI4 interface comes from a SmartConnect IP with a 512bits data interface.

 

Couls this be caused by parameters set in the smart connect IP?

I don't see any parameter in the BRAM controller AXI port that I could have messed up:

bram_ctrl_axi.png

 

Thank you again for looking into this.

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egatard
Visitor
Visitor
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Registered: ‎06-20-2018

I forgot to add:

The only AXI master to this BRAM controller is a CDMA IP.

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