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Registered: ‎09-19-2012


existing design which is based on xilinx Spartan-6  FPGA-XC6SLX16CSG342   , it is used for digital printer application in which image is printed on media based on resolution to be achieved  .
Following is the design scenario, discussed in breif
1). In our design we are using  Processor based SOM  and FPGA on our main controller Board . 
FPGA  and SOM are interface using the WEIM bus of which is a parallel bus having 
a). multiplexed : Address/Data Bus
b). CS-Chip Select  : active low .
c). RW-read/write : active low .  
d). LBA - Address latch en :  : active low . 
2). As in design there is no external memory, so  we have to use BRAM-IP as FIFO , the technique used is  2-Bucket technique to store the data in the FIFO( BRAM ) each Bucket is configured so that it can store 16(width) x1024(depth) x 16(total-BRAM IP) in standard FIFO MODE.  
3). DATA Interface: The data transfer from i.MX to FPGA is interrupt driven , i.e. when interrupt is sent from FPGA to  , which is generated after terminal count of Level-2 Bucket i.e. 1024 count value , on this value interrupt is send to processor to initiate the next Burst data write to FPGA ,  Burst length is of 16(bit word size) X (16384 -total number of words)  for one Bucket. 
4). Bucket-1 Level  write cycle: The individual BRAM write enable is generated by using address decoded module designed in FPGA  so that write enable is active  for individual BRAM during respective address mapped cycle. So sequential write operation takes place at Bucket level-1   but due to latency in the write cycle of 4-clk pulse the 4 data word are written as zero in the BRAM due to which empty and full flag are not used correctly .
5). Bucket-1  Read cycle:  Once the (Bucket-1 is full  and Bucket-2 Has reached the terminal count of 1024) , Data  read operation take place from Bucket-1, and written to  Bucket-2 but this read(Bucket-1)/write(Bucket-2) is concurrent all the 16-BRAM are read/written in parallel at 66.5MHz rate . 
6). Bucket-2  Read cycle:  The read operation is initiated by the resolution factor which is to be achieved on media i.e. we call it HRU (Horizontal Resolution Unit) which is regenerated at a rate of 27u sec during printing operation , at each HRU interrupt 16-Read Clocks are generated and 16-words are read out  from each BRAM and send on LVDS line to other FPGA board, the second board is also based on  Spartan-6 FPGA device , Bucket-2 BRAM directly interact with this board , so total of  64 READ operation in parallel  takes place from all the 16-BRAM which is 64 x 16 = 1024 
Note : 
1). The issue is related to the Empty and Full flag as there is Latency in generation of these flag the data is missed , and so during read cycle  are read as ZERO , due to which the output from Bucket-2  appear as shifted date with Zero in between data shift out cycle and which in turn make the image on media corrupt .
2). How the BRAM memory can be reset to all Zero value , if there is any work around without forcefully re-writing  ZERO . The  Reset provided on the BRAM block has been used but its purpose is to reset output buffer and wr/rd count value and not the memory location value .
3) Any solution for BRAM-IP as FIFO  usage is available in VHDL please let me know . 
4) One issue appears that the data is shifted by 128 Bits or 8 words due to which the image appear as corrupt 
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