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ali_farahany
Visitor
Visitor
438 Views
Registered: ‎02-18-2019

BRAM UTILIZATION PROBLEM

 

I have wrote a ram block forZYNQ-7020 FPGA. The issue is that its BRAM utilization is higher than my expectation. I expect 32 and 40 bram clock for this RAM Block but the utilization is higer.

 

RAM BLOCK:

`timescale 1ns/1ps
module dbram #
( parameter DWIDTH=18
, parameter AWIDTH=20
)
( input clk
, input we, sel0, sel1
, input [AWIDTH-1:0] addr
, input [AWIDTH-1:0] addr1
, input [DWIDTH-1:0] di
, output [DWIDTH-1:0] dout
, output [DWIDTH-1:0] dout1
);

reg [17:0] ram [0:40959];  // reg [17:0] ram [0:32767]; 
reg [DWIDTH-1:0] read_a;
reg [DWIDTH-1:0] read_a1;


always @(posedge clk)
begin
if (sel0 & we)
ram[addr[19:2]] <= di;
read_a <= ram[addr[19:1]];
read_a1 <= ram[addr1[19:1]];
end

assign dout = sel0 ? read_a : 32'b0;
assign dout1 = sel1 ? read_a1 : 32'b0;

endmodule

the Utilization:

utilization.png

 Actually i expect 32 and 40 BRAM block consequently. But as you seen it is 36 and 72 and it runs me out of resources.

 

 Could anybody help me?

0 Kudos
1 Reply
miker
Xilinx Employee
Xilinx Employee
425 Views
Registered: ‎11-30-2007

You can try the RAM_DECOMP synthesis attribute.  Please reference the Vivado Design Suite Synthesis User Guide (UG901; v2020.1; p 60).

forums_ram_decomp.png

In your case, you would want to modify the following line from:

reg [17:0] ram [0:40959];  // reg [17:0] ram [0:32767];

to:

(* ram_decomp = "power" *) reg [17:0] ram [0:40959];  // reg [17:0] ram [0:32767]; 

This will result in the following:

forums_ram_decomp_2.png

Please Reply, Kudos, and Accept as Solution.
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