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Scholar
Scholar
5,913 Views
Registered: ‎04-27-2010

BRAM connections change in implementation

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I have a design that uses a BRAM generated using the Vivado BRAM generator. The write and read ports are different clocks. If I look at the synthesized design the BRAM's ENARDEN is set to a constant. But in the implementation there is a new circuit that has been added (see below). I am now getting some warnings (see below). The new signals seem to be driven from the TREADY signal of a FIFO I have. But in my HDL the TREADY signal is just used to increment the BRAM read address. So I am not sure why its now connected to the RDEN signal.

Thanks

 

Untitled.png

 

[DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check - The RAMB36E1 system_i/audio_filter_0/U0/U_coeff_mem/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram has an input control pin system_i/audio_filter_0/U0/U_coeff_mem/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram/ENARDEN (net: system_i/audio_filter_0/U0/U_coeff_mem/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_sp.ram_ENARDEN_cooolgate_en_sig_31) which is driven by a register (system_i/audio_filter_0/U0/U_ip_fifo/U0/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.

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Xilinx Employee
Xilinx Employee
10,638 Views
Registered: ‎09-20-2012

Hi @beandigital

 

It looks like BRAM power optimization phase of opt_design is doing this change, you can use NoBramPowerOpt opt_design directive to prevent this change.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
5,912 Views
Registered: ‎08-01-2008
are you getting functional issue . I would like to know which version of IP and vivado tool you are using at your end . Check this related discussion
https://forums.xilinx.com/t5/7-Series-FPGAs/DRC-23-20-Rule-violation-REQP-1839-RAMB36-async-control-check/td-p/632362
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
10,639 Views
Registered: ‎09-20-2012

Hi @beandigital

 

It looks like BRAM power optimization phase of opt_design is doing this change, you can use NoBramPowerOpt opt_design directive to prevent this change.

Thanks,
Deepika.
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Scholar
Scholar
5,896 Views
Registered: ‎04-27-2010
Thanks for the reply. Can you tell me how I would do this in my xdc file? I tried using set_property "steps.opt_design.args.directive" "NoBramPowerOpt" [get_runs impl_1] but it said that the last argument wasn't supported.
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Xilinx Employee
Xilinx Employee
5,893 Views
Registered: ‎09-20-2012

Hi @beandigital

 

Run the below command from TCL console of open project

set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE NoBramPowerOpt [get_runs impl_1]

Thanks,
Deepika.
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Scholar
Scholar
5,890 Views
Registered: ‎04-27-2010

OK. But what if I want to have the command done automatically. I really would like it to be put into the xdc file.

Thanks

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Xilinx Employee
Xilinx Employee
5,887 Views
Registered: ‎09-20-2012

Hi @beandigital

 

No you cannot have this in XDC file.

 

This is Implementation setting, if you set it once it will stay until you change it (even if you close and reopen project)

Thanks,
Deepika.
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Scholar
Scholar
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Registered: ‎04-27-2010

OK I can see that it has changed the implementation settings. 

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