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Registered: ‎12-12-2019

BRAM memory generating for VC707 using xilixn vivado2019.2

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Hi,

i am generating BRAM memory using Xilinx vivado2019.1 tool for VC707 board.

I could see Total port A read latecy is 2 clock cycles usage in memory generating summery details  but when i generate memory using xilinx core generator i don see this issue.. does it make any effect on my FPGA design. Can you please tell me how to change read 2 clock cycle latency to 1 clock cycle..

 

Thanks,

Bhagavantha Reddy 

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Registered: ‎01-22-2015

bhagavantha.reddy@sifive.com 

In the Block Memory Generator wizard, unchecking "Primitives Output Register" and unchecking "Core Output Register" should give you are read-latency of 1.

BRAM_output_registers.jpg

Cheers,
Mark

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145 Views
Registered: ‎01-22-2015

bhagavantha.reddy@sifive.com 

In the Block Memory Generator wizard, unchecking "Primitives Output Register" and unchecking "Core Output Register" should give you are read-latency of 1.

BRAM_output_registers.jpg

Cheers,
Mark

View solution in original post

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Registered: ‎12-12-2019
hi Mark,

Thanks for your solution, Now i can able to change read clock latency to 1 clock cycle.

Thanks,
Bhagavantha Reddy