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Visitor kwjcoo
Visitor
250 Views
Registered: ‎07-22-2019

BRAM operation

Hello,

I just started to learn how to use BRAM. I made a simple project writing and reading to/from a BRAM. But on the simulation result, it is obvious that either I didn't write or read properly.  Was working on it hours but could not find an answer for it.

Following is the top module writing and reading from a BRAM 

module top(
    input start,
    input clk,
    input dina,
    output doutb,
    output reg finish
    );
    
    reg [3:0] addra;
    reg [3:0] addrb;
    reg [3:0] cnt;
    reg ena;
    reg wea;
    reg enb;
    reg write;
    wire [7:0] nomeaning;
    reg waitState;
    
    always @(posedge clk)
    begin
    if(!start)
    begin
        addra <= 0;
        addrb <= 0;
        cnt <= 0;
        write <= 0;
        finish <= 0;
        waitState <= 0;
        wea <= 0;
    end
    else
    begin
        if(write == 0)
        begin
            addra <= addra + 1;
            ena <= 1;
            wea <= 1;
            if(cnt == 15) 
            begin
                waitState <= 1;
                write <= 1;
            end
            else cnt <= cnt + 1;
        end
        else if(waitState == 0)
        begin
            wea <= 0;
            ena <= 0;
            addrb <= addrb + 1;
            cnt <= cnt - 1;
            enb <= 1;
            waitState <= 1;
            if(cnt == 0) 
            begin
                enb <= 0;
                finish <= 1;
            end
        end
        else if(waitState == 1)
        begin
            waitState <= 0;
        end
    end
    end
    
    blk_mem_gen_0 bufferram_i(
       .addra(addra),
       .clka(clk),
       .dina(dina),
       .douta(nomeaning),
       .ena(ena),
       .wea(wea),
       .addrb(addrb),
       .clkb(clk),
       .dinb(0),
       .doutb(doutb),
       .enb(enb),
       .web(0)
       );
                
endmodule

and the following is the testbench program

`timescale 1ns / 1ps

module tb();

    reg clk;
    reg [7:0] dataIN;
    wire [7:0] dataOUT;
    reg start;
    wire done;
    integer i;
    
    top top_i(
        .start(start),
        .clk(clk),
        .dina(dataIN),
        .doutb(dataOUT),
        .finish(done)
        );
        
    initial
    begin
        clk <= 1'b0;
        start <= 1'b0;
        
        #10
        start <= 1'b1;
        dataIN <= 8'b0000_0000;
        #10
        dataIN <= 8'b0000_0001;
        #10
        dataIN <= 8'b0000_0000;
        #10
        dataIN <= 8'b0000_0001;
        #10
        dataIN <= 8'b0000_0000;
        #10
        dataIN <= 8'b0000_0000;
         #10
         dataIN <= 8'b0000_0000;
         #10
        dataIN <= 8'b0000_0001;           
         #10
        start <= 1'b1;
        dataIN <= 8'b0000_0001;
        #10
        dataIN <= 8'b0000_0001;
        #10
        dataIN <= 8'b0000_0010;
        #10
        dataIN <= 8'b0000_0011;
        #10
        dataIN <= 8'b0000_0100;
        #10
        dataIN <= 8'b0000_0101;
         #10
         dataIN <= 8'b0000_0110;
         #10
        dataIN <= 8'b0000_0111;                             
     end
     
     always @(*)
     begin
        #1 clk <= ~clk;
     end
        
endmodule

The last is the screenshot of my simulationQ.png

Thanks in advance!

0 Kudos
2 Replies
Scholar u4223374
Scholar
238 Views
Registered: ‎04-26-2015

Re: BRAM operation

I think the problem is just that your "dina" and "doutb" signals in the top signal are only 1-bit.

Visitor kwjcoo
Visitor
223 Views
Registered: ‎07-22-2019

Re: BRAM operation

Thanks so much.

I thought I checked the file thoroughly, but apparently i didn't...

Thank you so much!