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Contributor
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Registered: ‎05-20-2015

BRAM read error and initialization using blk_mem_gen in VIVADO 16.3

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Hello,

 

I have a design that uses a dual port RAM. I am using the blk_mem_gen in VIVADO 16.3. Side B is written to by a my IP in PL and the other is read from by the Zynq processor.

I know I am writing the right data but when the Zynq reads it  there is, what it looks like bit 11 of the data bus that gets set randomly and gives me the wrong data.

 

Then I went and I created a simple design that uses a dual RAM and Zynq processor writing to one side and reading from the other. And I have the same problem. This tells me that my problem is in instantiation of the BRAM. At least I think.

1- Can somebody tell me if I am doing something wrong in instantiating the BRAM.

2- I see the BRAM has the capability to initialize it to a known pattern form a COE. But it is grayed out on the block design and I can not use it. Is it possible to use this feature?

 

Thanks,

Cherif

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Contributor
Contributor
1,430 Views
Registered: ‎05-20-2015

Hi,

 

Thanks for getting back to me.

I am using the BRAM in BRAM "controller mode" and I figured out that the pre-load is not supported. Although, it will be nice to have in the future.

As to my other problem, I have configured my RAM to just 4K but I was using using an address to write to to 8K, thus the overwrite because of wrapping around. So it is solved.

 

I have another question, I need to write separate bytes to each address. I assume I can control them using the web[3:0].  For example:

 

Address  xxx00 with   Web[0011] will write to  the 2 lower bytes of the word ( bytes: 1 and 2).

similarly

Address  xxx00 with   Web[1100] will write to  the 2 higher bytes of the word ( bytes: 3 and 2).

 

Is this correct?

 

Thanks,

Cherif

 

 

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Moderator
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Registered: ‎08-08-2017

Hi @chibane-mit

 

Please share the .xci file or the complete project  to check the BMG settings and reproduce this behavior at our end.

I presume the mode selected here is BRAM controller mode , the memory initialization is not supported in BRAM controller mode and hence the memory initialization field is grayed out. Most of the parameters are propagated from master. 

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Reply if you have any queries, give kudos and accept as solution
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0 Kudos
Highlighted
Contributor
Contributor
1,431 Views
Registered: ‎05-20-2015

Hi,

 

Thanks for getting back to me.

I am using the BRAM in BRAM "controller mode" and I figured out that the pre-load is not supported. Although, it will be nice to have in the future.

As to my other problem, I have configured my RAM to just 4K but I was using using an address to write to to 8K, thus the overwrite because of wrapping around. So it is solved.

 

I have another question, I need to write separate bytes to each address. I assume I can control them using the web[3:0].  For example:

 

Address  xxx00 with   Web[0011] will write to  the 2 lower bytes of the word ( bytes: 1 and 2).

similarly

Address  xxx00 with   Web[1100] will write to  the 2 higher bytes of the word ( bytes: 3 and 2).

 

Is this correct?

 

Thanks,

Cherif

 

 

View solution in original post

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Moderator
Moderator
1,402 Views
Registered: ‎08-08-2017

Hi @chibane-mit

 

Thanks for your findings.

 

Yes your understanding is correct. The byte write enable feature allows a single byte of the input data to be written to the selected address. Each write enable bit  web[3:0] enables the writing of eight data bits (a byte).

 

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Reply if you have any queries, give kudos and accepts as Solution

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Reply if you have any queries, give kudos and accept as solution
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