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Samosia
Newbie
Newbie
343 Views
Registered: ‎01-23-2021

BRAM read problem

I am using ZCU104 board, Vivado to program the device and ILA to evaluate created system. I encountered problem during reading content from BRAM.

BRAM configuration:

Mode: Stand Alone (address interface with 32 bits) - 2 clock cycles latency

Memory Type: True Dual Port Ram

Port A: Write First

Port B: Read First

(Write/Read width: 32, Write/Read depth: 256)

At first I write some values to the BRAM using port A and it looks ok (address changes on rising clock-edge). Fragment below: 

problem1.png

After that I read values from BRAM using port B (address changes on rising clock-edge). Fragment below, the same addresses like on previous picture:

problem2.png

I don't understand why reading value changes after every 4 clock cycle and not on every clock cycle when enable is on. This behaviour causes skipping proper data for most of the addresses. What can be the reason?

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1 Reply
hpbhat
Adventurer
Adventurer
173 Views
Registered: ‎02-08-2021

Hi,

Here, it looks like you are using different frequencies for CLKA & CLKB ports. 

You can open example design of Block memory Generator IP & run the simulation to check the behavior of the IP.

With Regards,

HPB

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