I am using ZCU104 board, Vivado to program the device and ILA to evaluate created system. I encountered problem during reading content from BRAM.
Mode: Stand Alone (address interface with 32 bits) - 2 clock cycles latency
Memory Type: True Dual Port Ram
Port A: Write First
Port B: Read First
(Write/Read width: 32, Write/Read depth: 256)
At first I write some values to the BRAM using port A and it looks ok (address changes on rising clock-edge). Fragment below:
After that I read values from BRAM using port B (address changes on rising clock-edge). Fragment below, the same addresses like on previous picture:
I don't understand why reading value changes after every 4 clock cycle and not on every clock cycle when enable is on. This behaviour causes skipping proper data for most of the addresses. What can be the reason?