12-04-2019 07:30 AM
Dear @venkata ,
I posted this question several time on this community but I got always ignored by Xilinx employees.
I really believe there is a BUG in the Ultrascale+ vcu118 xcvup9 board.
The Aurora 64bb core do not gets acvitated (channel_up and lane_up and s_axi_tx_tready stays always low).
This design works properly on Kintex-7 but when I migrate it to the Ultrascale (with proper constraints) it never works neither in Post-Synthesis or real FPGA operation.
The Aurora 64bb design is on the ultrascale constrained the FMC connector 33 (VITA 54.4)) on which it is plugged an FM-S14 card which connects the aurora to 4 SFP+ module. The following are the pin used to connect this card ot the FPGA (follwing FMC standard from card manual)
set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 121 - MGTYTXN3_121
set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 121 - MGTYTXP3_121
set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 121 - MGTYRXP3_121
set_property PACKAGE_PIN AJ46 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 121 - MGTYRXN3_121
set_property PACKAGE_PIN AH39 [get_ports "FMCP_HSPC_GBT1_0_N"] ;# Bank 121 - MGTREFCLK1N_121
set_property PACKAGE_PIN AH38 [get_ports "FMCP_HSPC_GBT1_0_P"] ;# Bank 121 - MGTREFCLK1P_121
I am sending to the SFP modules proper activation pins and I am performing a loop back test by placing a bridge on the sfp socket.
The Aurora is operating with 1 Lane in Duplex, Frame mode.
What to do with this?
12-20-2019 02:25 AM
Hi @mik3l3_hdl ,
Please follow the “Hardware Debug” section of the PG074 and check where design is failing .
Please try to run the design in simulation and check if you are seeing the channel and lane up .
Please try to run the design in loopback mode to remove all the issue related to the interfacing .
12-20-2019 07:12 AM
Dear @rkhatri ,
I finally managed to have the Aurora 64 working on the Ultrascale but still there is a PROBLEM.
The PROBLEM is that the Ultrascale Manual , as many other users with which i talked have noticed , as a lack of information regarding the location of the GTY. This is very troublesome and had me loss lot of time to figure out. I had to open the GTY transceiver IP and find those information inside it. But if one does not come up with ideas like this, then things become difficult with Ultrascale while with Virtex-7 or Kintex-7 this does not happen.
The location of the GTY transceivers is not explicitly related in any table of the latest version of the Ultrascale manual (2018: ug1224-vcu118-eval-bd.pdf, I kept looking but to me this was the latest version).
You guys of Xilinx should update this manual and provide explicit information about the GTY location as it has been done for the Virtex-7 VC707 manual (ug885_VC707_Eval_Bd.pdf) pag 34 Table 1-11 (I work with different FPGAs so I noticed the difference).
This is an issue which has to be solved once forever please. Also another think, I notice that you guys replied to this post almost 1 month later and would be nice to have faster response, specially for cases like my team which is investing a lot in Xilinx equipment.
Thanks a lot
01-30-2020 08:45 AM
thanks for your indications,
at the time I finally manageed to make it work but forgot to update you.
All was realated to the correct localization of the Transceivers, specifically the manual of the Ultrascale was missing that information (the localization in X#Y# coordinateds of transceiver - Quads. This information is clearly stated in the manuals of Virtex-7 and Kintec kc705.
You guys should update the Ultrascale manuals.