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Observer
Observer
14,156 Views
Registered: ‎05-21-2008

Beginner: adding an "and" gate to an EDK project, to combine 2 xps_emc_mch banks, howto

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  In a fairly large project using the xps_emc_mch controller controlling static ram, we need to combine two bank's worth of _oen<BN> signals and put that combination to a xilinx pin.  I generally understand the ucf file and mhs file formats and concepts.  We are adding a second bank of memory, and must kludge backwards to existing hardware.

 

   I'm rather raw at this, so I've been googling and reading and asking other local Xilinx engineers, and the answers online and in person have been rather vague.

 

   Has anyone done this?  Is there an Manual that I can RTFM that would cover this? I've not found anything that covers something this simple, yet this complex.  If it were our IP, we could do it in the "user logic" section, I've been told.  But when I say "It is a Xilinx IP" I get blank stares.

 

   I tried creating a new IP in XPS, but it doesn't want to let me do something this simple.  It wants to do complex bus controllers and the like.

 

   help, please.

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Observer
Observer
20,955 Views
Registered: ‎05-21-2008

I finally have it figured out.  The documentation you pointed me to did not click with me.  My need was much too simple and the solutions much too complex. 

 Here is the answer for adding an "and" gate to EDK and connecting it to the MEM_OEN vector output from the emc block:

 

1) Create a simple "and_wrapper.vhd", place in your hdl directory in your project main directory.  here is the contents of the and_wrapper.vhd.

-------------------------------------------------------------------------------
-- and_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity AND_ent is
port(    x: in std_logic_vector(0 to 1);
    F: out std_logic
);
end AND_ent; 


architecture STRUCTURE of AND_ent is
begin
 
    F <= x(0) and x(1);

end architecture STRUCTURE;

 

2) using "create or import a peripheral", import the existing peripheral into the project.  I called it "and_ent".  This is too simple of a wrapper to show up in your system when you add it to the project.

 uncheck the Bus screen, and the interrupt screen.  answer OK to the questions.

 

3) Under   the IP catalog screen, it will show up in Project Local Pcores, under User.  Add the ip to your project.

 

4) increase the number of banks in the emc controller.  then click on the "bit image" icon.  You'll get an error, but this rebuilds the wrapper so you can use the and gate later.  The EDK can't handle too many things changing at once (unless perhaps you do a clean build).

 

4) in your .mhs file add the following lines (but change signal names to protect the innocent)

BEGIN and_ent
 PARAMETER INSTANCE = oen_and_gate
 PORT x = i_sram_oen
 PORT F = i_sram_oen_and
END

 

The i_sram_oen is the output enable from the emc. In our .mhs file it is listed:

 

 PORT Mem_OEN = i_sram_oen

 

the outside name is in the mhs file as follows.  modify it to have the and output.  If there is a vector statement there, remove it from the line:

 PORT sram_oen = i_sram_oen_and, DIR = O

 

the ucf file lists the sram_oen.  you'll have to touch it as it picked up the vector from the earlier wrapper rebuild, remove the <0>

NET "sram_oen"       LOC = "AK28"  | IOSTANDARD = LVCMOS33;
 

 

This completes the exercise.  The Zen of Xilinx is now complete.

 

I give permission to use this information in any publication or any way you wish, freely.

 

I am certain the wrapper needs a touch more to show up in the EDK, but I'm still learning.  Perhaps a non-zen person can complete that part of the wrapper puzzle for me.

View solution in original post

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Scholar
Scholar
14,151 Views
Registered: ‎02-27-2008

w,

 

'How can something so simple, be so difficult' is what you are saying.  Well, EDK tries to hide all the complexities of pins, constraints, etc. from the user, and in so doing, the inherent flexibility of the FPGA device is lost.

 

If you have Xilinx built IP, then those IP blocks have some flexibility, but in the EDK environment, again, they become inflexible.

 

If you want complete flexibility, then you are pretty much constrained to stay within the logic framework of the ISE tools, and do everthing in HDL, and constraint files.

 

You may proceed to hack away at this problem in EDK (as you have described), and you might make something work, but I advise against it, as you are going to be fighting the tools all the way 'there' (wherever 'there' is).

 

Adding your own IP is fairly well covered, and adding another IP block, from the existing list of IP blocks is also well covered.

 

Sounds like you are making a custom memory interface, in which case the Memory Interface Generator is where to go for that, and that becomes a project unto itself.  Once you have made that block work, then you could then import it back into EDK and use your memory interface instead of the one that is in use now...

 

If it is as simple as one AND gate, and one pin, then you can do this with FPGA_Editor, where you can change and add anything, bit by bit, wire by wire, LUT by LUT, pin by pin.  If it is as simple as one 2 input AND gate, and one pin, then using FPGA_Editor will get you there quickly (it is after all, a What You See Is What You Get editor for the device), but it leads to unmaintainable designs (its use is required every time, as the original description has no extra AND gate in it).  FPGA_Editor is great to find the cause of a problem, probe a node, or test a quick fix, but it is not the way to maintain a design intended to be put into production.

 

The frustration is that "such a simple change" to a block doesn't seem to be complicated, but to the tools, even one wire, or one pin, represents a start from scratch exercise:  how to place it, how to constrain it, and it becomes something new.

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
Observer
14,148 Views
Registered: ‎05-21-2008

 

 we aren't exactly doing a custom interface.  just a small modification.  We just want to add and and gate.

 

  I've stumbled across a project where someone did something similar to what I want to do. I'm trying to understand the technique now.  Once I get it, if I can remember to get back on this forum, I'll share it.

 

   The Xilinx documentation on adding IP's only covers complex IP's not adding small logic to an EDK system.  There don't appear to be any simple IP's that can be added to such a system, the "drop down" import menu never shows anything, and the Xilinx documentation is silent on where to get information on this.  a system 'find . -name "xxx" ' type of search doesn't yield much either.  However, that is SOP, no problem for me.

 

   I've been working with Xilinx EDK for software development (not hardware) since 6.1.  You'd think I'd have learned better by now.  At least most of the software build/debug tools generally work most of the time now in 10.1. (the previous best environment was 8.2)  The 11.1 Xilinx licensing handler changes froze my client's development environment at 10.1.

 

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Xilinx Employee
Xilinx Employee
14,141 Views
Registered: ‎08-13-2007

You may want to check out the XPS util_vector_logic core (e.g. %XILINX_EDK%\hw\XilinxProcessorIPLib\pcores\util_vector_logic_v1_00_a). The datasheet is in the doc subdirectory.

 

It was designed to allow simple glue logic to be supported in an EDK system. You can use SAV (System Assembly View) or edit the mhs file appropriately to add this in. Obviously this makes sense at the top-level of an embedded processing system and not inside another core, but it can be a useful approach for some cases.

 

bt

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Xilinx Employee
Xilinx Employee
14,139 Views
Registered: ‎08-13-2007

XAPP924 is an example where this core was used for a simple system modification (invert a signal).

http://www.xilinx.com/support/documentation/application_notes/xapp924.pdf (Reference System: Using the OPB EPC with the SMSC LAN 91C111 Controller)
Replace .pdf with .zip for the design files

 

bt

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Highlighted
Observer
Observer
20,956 Views
Registered: ‎05-21-2008

I finally have it figured out.  The documentation you pointed me to did not click with me.  My need was much too simple and the solutions much too complex. 

 Here is the answer for adding an "and" gate to EDK and connecting it to the MEM_OEN vector output from the emc block:

 

1) Create a simple "and_wrapper.vhd", place in your hdl directory in your project main directory.  here is the contents of the and_wrapper.vhd.

-------------------------------------------------------------------------------
-- and_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity AND_ent is
port(    x: in std_logic_vector(0 to 1);
    F: out std_logic
);
end AND_ent; 


architecture STRUCTURE of AND_ent is
begin
 
    F <= x(0) and x(1);

end architecture STRUCTURE;

 

2) using "create or import a peripheral", import the existing peripheral into the project.  I called it "and_ent".  This is too simple of a wrapper to show up in your system when you add it to the project.

 uncheck the Bus screen, and the interrupt screen.  answer OK to the questions.

 

3) Under   the IP catalog screen, it will show up in Project Local Pcores, under User.  Add the ip to your project.

 

4) increase the number of banks in the emc controller.  then click on the "bit image" icon.  You'll get an error, but this rebuilds the wrapper so you can use the and gate later.  The EDK can't handle too many things changing at once (unless perhaps you do a clean build).

 

4) in your .mhs file add the following lines (but change signal names to protect the innocent)

BEGIN and_ent
 PARAMETER INSTANCE = oen_and_gate
 PORT x = i_sram_oen
 PORT F = i_sram_oen_and
END

 

The i_sram_oen is the output enable from the emc. In our .mhs file it is listed:

 

 PORT Mem_OEN = i_sram_oen

 

the outside name is in the mhs file as follows.  modify it to have the and output.  If there is a vector statement there, remove it from the line:

 PORT sram_oen = i_sram_oen_and, DIR = O

 

the ucf file lists the sram_oen.  you'll have to touch it as it picked up the vector from the earlier wrapper rebuild, remove the <0>

NET "sram_oen"       LOC = "AK28"  | IOSTANDARD = LVCMOS33;
 

 

This completes the exercise.  The Zen of Xilinx is now complete.

 

I give permission to use this information in any publication or any way you wish, freely.

 

I am certain the wrapper needs a touch more to show up in the EDK, but I'm still learning.  Perhaps a non-zen person can complete that part of the wrapper puzzle for me.

View solution in original post

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